Semiconductor Etching via Selective Epitaxial Growth Hard Masks
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Solution Overview
Problem
Conventional photolithography techniques struggle to produce small critical dimensions (CDs) in semiconductor devices due to limitations in scanner resolution and material etch selectivity, leading to defects in features like trench and contact hole formation in advanced semiconductor fabrication processes.
Innovation Solution
A method involving the formation of hard mask patterns on a semiconductor base material, followed by the deposition of material layers using selective epitaxial growth (SEG) to create openings with dimensions smaller than the distance between adjacent hard mask patterns, allowing for precise etching of the semiconductor base material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional photolithography techniques are used with KrF or ArF lasers, then the photosensitive material layer can be exposed and developed to form micro-patterns, but the critical dimension precision deteriorates as line width decreases below 100 nm due to scanner resolution limits
Solution Approach 1:
The patent divides the patterning process into multiple stages: first forming a coarse pattern using conventional photolithography, then using selective epitaxial growth to create material layers that define the final precise critical dimensions. This segmentation allows each stage to optimize for its specific function, achieving sub-40 nm precision that exceeds scanner capabilities.
Solution Approach 2:
The patent introduces a hard mask layer and selectively grown material layers as intermediaries between the photolithography exposure and the final etching process. These intermediate layers serve as precise templates that transfer the pattern with higher accuracy than direct photolithography, enabling critical dimensions smaller than the scanner's resolution limit.
2Manufacturing precision
If the scanner resolution is improved to achieve smaller critical dimensions, then the manufacturing cost and process complexity increase significantly
Solution Approach 1:
The patent changes the physical parameters of the patterning process by transitioning from direct optical exposure to a multi-step process involving hard mask formation and selective epitaxial growth. By controlling the thickness and composition of grown material layers, precise critical dimensions are achieved without requiring advanced scanner resolution, thus avoiding the associated cost and complexity increases.
3Manufacturing precision
If photolithography is used to form small critical dimensions, then the etching process can proceed, but defects such as bridges and scum are generated due to resolution limits
Solution Approach 1:
The patent performs preliminary patterning actions by forming hard mask patterns and selectively growing material layers before the final etching step. This preliminary structuring creates well-defined openings that prevent bridge formation and scum generation during etching, significantly reducing defects in RCAT, SAC, and contact plug fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the fabrication of semiconductor devices with critical dimensions smaller than those achievable through conventional photolithography, improving the precision and reducing defects in features like trenches and contact holes, particularly in advanced processes such as RCAT and SAC.
Implementation Method 1
forming material layers covering the lateral and top surfaces of the hard mask patterns to form openings between adjacent hard mask patterns
Data Source
AI summary
A method of fabricating a semiconductor device comprising a method of forming an etching mask used for etching a semiconductor base material is disclosed. The method of fabricating a semiconductor device comprises forming hard mask patterns on a semiconductor base material; forming material layers covering the lateral and top surfaces of the hard mask patterns to form openings between adjacent hard mask patterns, wherein the width of each opening is smaller than the distance between adjacent hard mask patterns; and etching the semiconductor base material using the hard mask patterns and material layers as an etching mask.