Semiconductor Integrated Circuit Fail Path Detection
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Solution Overview
Problem
Conventional semiconductor integrated circuits face challenges in efficiently detecting failure paths due to numerous possible circuits, leading to increased analysis time and reduced productivity and efficiency.
Innovation Solution
A semiconductor integrated circuit with a data register and comparing units that generate and compare write and read expectation values with actual data during a test mode, allowing for the detection of failures and narrowing the analysis range of potential failure paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional testing methods are used to test semiconductor integrated circuits, then the circuit can be tested for operational normality, but the analysis time to detect failure paths increases significantly
Solution Approach 1:
The patent divides the failure detection process into multiple independent comparison stages by segmenting the data path into distinct segments (first data path from data input buffer to write driver, second data path from write driver to data sense amplifier). Each segment is tested separately with dedicated comparing units, allowing parallel analysis and reducing overall detection time while maintaining comprehensive coverage of all possible failure paths.
2Reliability
If comprehensive testing of all possible failure paths is performed, then complete failure detection is achieved, but productivity and efficiency are lowered
Solution Approach 1:
The patent implements preliminary action by pre-storing expected data values in the data register before actual writing occurs. The data register stores the data that should be written into the memory cell and the data that should be read back, allowing the comparing units to immediately compare actual results against predetermined expectations without requiring comprehensive re-testing of all paths.
Solution Approach 2:
The patent creates a copy of the expected data path behavior through the data register, which stores replica data values representing what should occur during normal operation. This copy allows the comparing units to detect failures by comparing actual data against the stored expected values, eliminating the need to re-trace all possible paths during analysis.
3Loss of time
If the data register stores expected values and comparing units compare actual data against these expectations, then failure paths can be quickly identified, but the device complexity increases
Solution Approach 1:
The patent applies universality by designing the data register and comparing units to serve multiple functions: the data register stores both write expectation values and read expectation values, and the comparing units can compare data at multiple stages (write driver output and data sense amplifier output). This multi-functional design reduces the need for separate dedicated circuits for each comparison task, thereby limiting the increase in device complexity while maintaining fast failure detection.
Data Source
AI summary
Disclosed is a semiconductor integrated circuit that allows a fail path to be detected. A semiconductor integrated circuit as described herein can be configured to include a data register that can receive input data to generate and store a write expectation value and a read expectation value, during a period in which a test mode is activated, a first comparing unit that compares write data written in a memory cell with the write expectation value, and a second comparing unit that compares read data read from the memory cell with the read expectation value.