Semiconductor Fault-Scan Circuit for Pin-Limited Malfunction Localization
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Solution Overview
Problem
Conventional semiconductor devices face challenges in detecting and specifying the point of setup violations due to limited pins, which leads to bundled error signals and inability to accurately identify the source of malfunctions, and often induce malfunctions in subsequent stages.
Innovation Solution
A semiconductor device with a plurality of logic circuits and judging circuits, including a first register, delay means, comparator, and scanning means, which allows for the transmission of error signals to specify the point of malfunction by making the second register a shift register to hold comparison results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple error signals from different circuits are bundled together using an OR tree, then the number of pins required is reduced, but the ability to specify the point where setup violation occurs is lost
Solution Approach 1:
The patent divides the error signal detection into multiple independent judging circuits, each responsible for a specific logic circuit. Each judging circuit outputs an error signal that can be independently tracked. The scanning means segments the error signal transmission path, allowing sequential examination of each judging circuit's output without requiring separate pins for each error signal source.
2Reliability
If a Razor circuit is used to detect setup violations, then timing constraints can be actively detected, but the complexity of the circuit increases and pins are required for error signal output
Solution Approach 1:
The judging circuits are designed to serve multiple functions: they detect setup violations, specify the location of malfunctions, and interface with the scanning means for error signal transmission. This multi-functionality reduces the need for separate dedicated components for each function, thereby managing complexity while maintaining detection reliability.
3Measurement precision
If error signals are transmitted through multiple pins to specify malfunction points, then the accuracy of malfunction specification is improved, but the number of pins required increases which is limited in semiconductor devices
Solution Approach 1:
The patent transitions from a spatial distribution of error signals across multiple pins to a temporal scanning sequence. The scanning means examines error signals from different judging circuits in sequence over time, allowing the system to identify the source of malfunction through time-multiplexed examination rather than simultaneous multi-pin output.
Data Source
AI summary
An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.