Semiconductor Fault Localization Using Scanable Error Registers
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Solution Overview
Problem
Conventional semiconductor devices face challenges in detecting and specifying the point of setup violations due to limited pins, which leads to bundled error signals and inability to accurately identify the circuit causing the malfunction, resulting in potential induction of malfunctions in subsequent stages and variability in detection conditions.
Innovation Solution
A semiconductor device with multiple logic circuits and judging circuits, including a first register, delay means, a second register, a comparator, and scanning means, which allows for error signal transmission and comparison to specify the point of malfunction by converting the second register into a shift register to transmit error signals and hold comparison results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If multiple error signals from different circuits are bundled by an OR tree to output error signals, then the number of pins required is reduced, but the ability to specify the point at which setup violation occurs is lost
Solution Approach 1:
The patent divides the error signal detection into multiple independent judging circuits, each associated with a specific logic circuit. Each judging circuit independently detects setup violations in its corresponding logic circuit and outputs a dedicated error signal. This segmentation allows each error signal to be independently tracked and specified, resolving the contradiction between reducing pin count and maintaining malfunction point specification capability.
2Reliability
If a Razor circuit is used to detect setup violations by comparing flip-flop and latch outputs, then timing constraints can be actively detected, but the complexity of the circuit increases
Solution Approach 1:
The patent extracts the essential function of setup violation detection from the complex Razor circuit by using a simplified judging circuit that only compares the output of the logic circuit with the expected value from the delay means. This extraction maintains the core detection capability while significantly reducing circuit complexity, as it eliminates the need for both flip-flop and latch circuits while preserving the ability to detect timing constraints.
Solution Approach 2:
The patent uses a copy of the logic circuit output fed through delay means to create an expected value signal. This copying approach allows the judging circuit to compare actual output with what should have been output if timing were correct, enabling setup violation detection without requiring the complex dual-register Razor structure.
3Measurement precision
If error signals are detected and restored in conventional circuits, then setup violations can be identified, but malfunctions may be induced in subsequent stages
Solution Approach 1:
The patent applies local quality by making each judging circuit independent and associated with a specific logic circuit. Each judging circuit only monitors its own logic circuit's output and does not affect subsequent stages. This localized detection approach allows setup violations to be detected without creating malfunctions in subsequent stages, as each circuit operates independently with dedicated error signals that do not propagate beyond their respective logic circuits.
Data Source
AI summary
An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.