Molded Semiconductor Package Filler Distribution
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Solution Overview
Problem
High wire density in semiconductor packages leads to filler material screening out near die edges, causing a mismatch in thermal expansion coefficients (CTE) between the mold compound, die, and substrate, resulting in crack formation and reliability issues.
Innovation Solution
Injecting mold compound through multiple openings around the package substrate, ensuring a higher concentration of filler material under and adjacent to wire bonds, thereby maintaining consistent CTE across the semiconductor package.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If wire density is increased to accommodate higher pin count, then electrical connectivity is improved, but filler material is screened out in certain regions causing CTE mismatch and crack formation
Solution Approach 1:
The patent applies local quality by varying the filler material particle size distribution in different regions of the mold compound. Specifically, larger filler particles (e.g., 40-70 microns) are used in regions with high wire density near the die to prevent screening, while smaller particles (e.g., 5-20 microns) are used in regions with lower wire density. This regional variation in filler characteristics ensures adequate CTE matching in all areas without compromising reliability.
2Stability of the object's composition
If uniform filler material distribution is maintained, then CTE consistency is improved, but wire density prevents filler flow in high-density regions
Solution Approach 1:
The patent applies parameter changes by modifying the filler material particle size parameter in response to wire density variations. In high wire density regions, larger filler particles are used to overcome the screening effect caused by closely spaced wires. The patent specifies using filler particles with sizes ranging from 40-70 microns in high-density areas, which can navigate through the wire gaps more effectively than smaller particles, thereby achieving adequate filler distribution and CTE consistency.
3Manufacturing precision
If smaller filler particles are used, then CTE matching precision is improved, but filler screening by wires increases
Solution Approach 1:
The patent applies local quality by using different filler particle size ranges in different regions. In regions with high wire density where screening is problematic, larger filler particles (40-70 microns) are used. In regions with lower wire density where screening is less of an issue, smaller filler particles (5-20 microns) can be used to achieve better CTE matching precision. This regional differentiation resolves the contradiction between CTE precision and filler screening.
4Object-affected harmful factors
If larger filler particles are used, then filler screening is reduced, but CTE matching precision decreases
Solution Approach 1:
The patent resolves this contradiction by applying local quality - using larger filler particles (40-70 microns) only in specific regions with high wire density where screening is the dominant problem, while using smaller particles (5-20 microns) in regions where CTE matching precision is the primary concern. This spatially differentiated approach allows each region to have optimized filler characteristics for its specific conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method prevents filler material screening and maintains consistent CTE, reducing the likelihood of crack formation and enhancing the reliability of semiconductor packages by ensuring a uniform filler distribution.
Implementation Method 1
As part of the molding process, the mold compound, including the filler material, is flowed across a top surface of the die contained in the semiconductor package.
Implementation Method 2
the regions of mold compound near the die edges may have filler material screened out
Data Source
AI summary
An integrated circuit is attached to a package substrate. The integrated circuit is electrically connected to the package substrate using a plurality of bond wires connected between a plurality of bond posts and a plurality of bond pads. A first plurality of the bond pads are along a first side of the integrated circuit and coupled to a first plurality of the bond posts with a first plurality of the bond wires. A second plurality of the bond pads are along a second side of the integrated circuit and coupled to a second plurality of the bond posts with a second plurality of the bond wires. Mold compound is injected through a plurality of openings in the package substrate. A first opening is between the first plurality of bond posts and the first side. A second opening is between the second plurality of bond posts and the second side.