Semiconductor Fin Structure Planarization via Laser Annealing
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Solution Overview
Problem
Nonplanar surfaces in semiconductor devices can lead to physical and electrical defects due to incomplete removal of excess material during chemical-mechanical planarization, causing yield reduction and performance issues.
Innovation Solution
The method involves forming fin structures with varying densities in different areas of a substrate, followed by laser annealing to convert amorphous silicon layers into crystalline silicon layers, which are then polished using CMP to achieve flat surfaces, with controlled removal rates to ensure uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical-mechanical planarization is performed on areas with different fin structure densities, then material removal occurs, but non-uniform polishing results in residual material and surface defects
Solution Approach 1:
The patent applies preliminary laser annealing to convert amorphous silicon to crystalline silicon in high-density fin areas before planarization. This pre-treatment modifies the material properties in advance to ensure uniform polishing behavior during subsequent CMP, resolving the non-uniformity issue caused by varying fin densities
Solution Approach 2:
The patent changes the physical state parameter of silicon from amorphous to crystalline through laser annealing in specific areas. This parameter change alters the polishing characteristics of the material, enabling uniform removal rates across areas with different fin structure densities during chemical-mechanical planarization
2Reliability
If excess material is deposited on back-end structures, then coverage is improved, but incomplete removal by planarization causes process-induced defects
Solution Approach 1:
Laser annealing is performed as a preliminary step before planarization to convert amorphous silicon to crystalline silicon in high-density areas. This pre-treatment ensures that subsequent CMP can completely remove excess material without leaving residuals, preventing process-induced defects while maintaining proper material coverage
Solution Approach 2:
The patent replaces part of the mechanical planarization process with laser annealing treatment. Instead of relying solely on mechanical CMP to remove all excess material, the laser treatment pre-modifies the material to facilitate complete and uniform removal, reducing residual material and preventing defects
3Adaptability or versatility
If non-uniform pattern density exists in different areas, then device functionality is maintained, but polishing uniformity deteriorates
Solution Approach 1:
The patent applies different treatments to different areas based on their local characteristics. High-density fin areas undergo laser annealing to convert amorphous silicon to crystalline silicon, while low-density areas retain amorphous silicon. This local differentiation ensures uniform polishing across the entire substrate despite varying pattern densities
Solution Approach 2:
The patent selectively changes the physical state parameter of silicon in high-density areas through laser annealing. By converting amorphous silicon to crystalline silicon locally in high-density fin areas, the polishing characteristics are modified to match low-density areas, achieving uniform polish across the substrate
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively addresses the defect issue by ensuring flat surfaces across different areas, enhancing device performance and yield by preventing shorts and opens, and allowing for more precise control over the planarization process.
Implementation Method 1
Part of the amorphous silicon layer which is disposed in the first area is annealed to form a crystalline silicon layer by a laser
Data Source
AI summary
A manufacturing method of a semiconductor device is provided. The manufacturing method includes the following steps. A plurality of fin structures are formed in a first area and a second area of a substrate. A first density of the fin structures in the first area is lower than a second density of the fin structures in the second area. A gate dielectric layer is formed on the fin structures. An amorphous silicon layer is formed on the gate dielectric layer and the fin structures in the first area and the second area. Part of the amorphous silicon layer which is disposed in the first area is annealed to form a crystalline silicon layer by a laser. The crystalline silicon layer disposed in the first area and the amorphous silicon layer disposed in the second area are polished.