Semiconductor Fine Pattern Formation via Spacer Etching
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Solution Overview
Problem
Current photolithography processes struggle to form fine patterns with widths smaller than their resolution limitations, leading to difficulties in producing high-density semiconductor devices and increased costs due to the need for both narrow and wide patterns.
Innovation Solution
A method involving the formation of hardmask patterns with varying intervals, spacers, and gap-filling patterns to simultaneously create narrow-width and wide-width patterns using a trimming process, allowing for the patterning of underlying layers to achieve patterns with widths beyond photolithography resolution limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If photolithography process is used to form narrow patterns, then pattern width can be reduced, but manufacturing precision deteriorates when width is below resolution limitation
Solution Approach 1:
The pattern formation process is segmented into multiple stages: first forming hardmask patterns at intervals, then forming spacers on sidewalls, and finally forming gap-filling patterns in the gaps between spacers. This segmentation allows each stage to contribute to the final narrow pattern dimensions, achieving precision below photolithography resolution limits by combining multiple coarser steps.
Solution Approach 2:
The invention transitions from two-dimensional photolithography patterning to three-dimensional spacer formation. By forming spacers on the sidewalls of hardmask patterns and filling gaps between spacers, the process utilizes vertical dimension (spacer height) to control horizontal pattern dimensions, achieving sub-resolution precision through dimensional transformation.
2Adaptability or versatility
If both narrow and wide patterns are formed using conventional photolithography, then process complexity increases, but manufacturing cost and time increase
Solution Approach 1:
The spacer formation and gap-filling process serves multiple functions simultaneously: it defines narrow patterns in first regions while preserving wide patterns in second regions, acts as an etch mask for subsequent processing, and enables different pattern widths from a single photolithography step. This multi-functionality eliminates the need for separate processing lines for narrow and wide patterns.
Solution Approach 2:
The process applies different treatments to different regions: in first regions, gap-filling patterns are formed to create narrow patterns, while in second regions, the original hardmask patterns are maintained as wide patterns. This local differentiation allows simultaneous formation of multiple pattern types without increasing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the simultaneous formation of fine and wide patterns, simplifying the semiconductor device fabrication process and reducing costs by allowing for the creation of patterns with widths smaller than the photolithography resolution, thereby improving the efficiency and density of semiconductor devices.
Implementation Method 1
The trimming process can comprise isotropically etching the gap-filling pattern exposed by the trimming mask pattern and the spacers adjacent to the exposed gap-filling pattern to expose sidewalls of the upper mask pattern and the gap-filling pattern
Implementation Method 2
forming spacers on both sidewalls of each of the hardmask patterns
Implementation Method 3
patterning the underlying layer using the gap-filling patterns and the hardmask patterns as an etch mask to simultaneously form narrow-width patterns on the first region and wide-width patterns on the second region
Data Source
AI summary
A method of forming fine patterns in a semiconductor device includes forming narrow-width patterns in a first region and wide-width patterns in a second region, where the widths of the narrow-width patterns are smaller than the resolution limitations in a photolithography process used to make the semiconductor device. The first and second regions may comprise cell array regions, with memory cells in the first region and peripheral circuits for operating the memory cells in the second region. The semiconductor device can be, for example, a NAND FLASH memory device. The semiconductor memory device can be variously classified according to the type of memory cells to be integrated in the cell array region, e.g., a DRAM, an SRAM, a PRAM, a RRAM, an MRAM, and a FRAM. In other embodiments, a MEMS device, an optoelectronic device, or a processor, such as CPU or DSP, may be provided on the semiconductor substrate.