Semiconductor Device Flat Channel Region High Frequency Operation
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high operating frequencies beyond 3 to 4 GHz due to limitations in reducing transistor size and increasing drain current, making it difficult to realize high-speed devices that can operate at frequencies of 10 GHz or more.
Innovation Solution
The development of a semiconductor device with a highly flat channel region surface, low contact resistance, and optimized electrode materials and structures, including the use of metal silicides with specific work functions, to enhance drain current and reduce series resistance, allowing for higher operating frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the size of semiconductor element is reduced, then the capacitance decreases and signal transmission speed increases, but the drain current cannot be increased and operating frequency improvement is impeded
Solution Approach 1:
The patent applies local quality by creating a highly flat channel region surface (peak-to-valley value ≤0.3 nm over 2 nm length) specifically in the channel area, while maintaining normal surface characteristics elsewhere. This localized flatness improvement directly enhances carrier mobility and drain current in the critical conduction path without requiring overall device size increase, thus resolving the contradiction between miniaturization and current maintenance.
Solution Approach 2:
The patent changes the surface flatness parameter of the channel region from conventional values (typically >1 nm peak-to-valley) to an extremely flat state (≤0.3 nm peak-to-valley over 2 nm). This parameter change fundamentally alters the carrier transport characteristics, enabling high drain current density even in miniaturized devices, thereby achieving both small size and high current simultaneously.
2Speed
If the size of semiconductor element is reduced to its limit, then further size reduction is impossible, but increasing drain current becomes difficult and operating frequency cannot be improved
Solution Approach 1:
The patent focuses quality improvement locally in the channel region by achieving extreme surface flatness (≤0.3 nm peak-to-valley over 2 nm) specifically where carriers flow, rather than improving overall device dimensions. This localized enhancement maximizes carrier mobility and drain current density within the constrained miniaturized geometry, enabling operating frequencies of 10 GHz or more despite size limits.
Solution Approach 2:
The patent employs composite material structures including metal silicide electrodes with specific work functions (first metal silicide for n-channel, second metal silicide for p-channel) combined with the highly flat channel region. This composite approach optimizes both contact characteristics and channel transport, achieving high drain current and transconductance in miniaturized devices for GHz-range operation.
3Quantity of substance
If conventional electrode materials and structures are used, then manufacturing is simpler, but contact resistance and series resistance are high reducing drain current
Solution Approach 1:
The patent applies local quality by selecting specific metal silicide materials for electrode-contact interfaces based on the channel type (n-channel or p-channel). The first metal silicide is used for n-channel devices and the second for p-channel devices, optimizing the work function match locally at each contact interface. This localized material optimization minimizes contact resistance and series resistance, enhancing drain current without complicating the overall manufacturing process.
Solution Approach 2:
The patent changes the material parameter (work function) of the electrode materials by selecting specific metal silicides with appropriate work functions for different channel types. This parameter change optimizes the energy band alignment at contacts, reducing Schottky barrier heights and contact resistance, thereby increasing drain current while maintaining manufacturing feasibility through standard silicide formation processes.
Data Source
AI summary
In a semiconductor device, the degree of flatness of 0.3 nm or less in terms of a peak-to-valley (P-V) value is realized by rinsing a silicon surface with hydrogen-added ultrapure water in a light-screened state and in a nitrogen atmosphere and a contact resistance of 10−11 Ωcm2 or less is realized by setting a work function difference of 0.2 eV or less between an electrode and the silicon. Thus, the semiconductor device can operate on a frequency of 10 GHz or higher.