3D Semiconductor Fuse Circuit Sharing for TSV Replacement
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Solution Overview
Problem
Current three-dimensional semiconductor apparatuses face inefficiencies in managing fuse information for replacing failed through-silicon vias (TSVs), which affects the degree of integration and chip area utilization.
Innovation Solution
A semiconductor apparatus is designed with a transmission control signal generation unit, a fuse signal transmission unit, and reception control signal generation units to synchronize clock signals and transmit fuse information efficiently across stacked chips, allowing for TSV selection and replacement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fuse circuit is disposed in each of the stacked chips to store TSV status information, then TSV replacement capability is improved, but chip area efficiency deteriorates
Solution Approach 1:
The patent merges the fuse circuits from multiple stacked chips into a single shared fuse circuit located in one chip. This allows all chips to share the same TSV status information storage resource, eliminating the need for separate fuse circuits in each chip and thereby improving chip area efficiency while maintaining TSV replacement capability.
Solution Approach 2:
The shared fuse circuit serves as a universal resource for all stacked chips, enabling a single circuit to perform the function of storing TSV status information for the entire 3D semiconductor apparatus. This multi-functional approach allows any chip to access the fuse information needed for TSV replacement without requiring dedicated circuits in each chip.
2Quantity of substance
If the number of TSVs is increased to achieve higher degree of integration, then integration density is improved, but the complexity of managing fuse information deteriorates
Solution Approach 1:
The patent segments the management of fuse information by introducing a master chip that centrally manages the shared fuse circuit and slave chips that access the fuse information under coordination. This segmentation of management roles simplifies the complexity of managing fuse information for a large number of TSVs by providing a hierarchical control structure.
Solution Approach 2:
The master chip acts as an intermediary between the slave chips and the shared fuse circuit. It controls access to the fuse information, manages the decoding of fuse data, and coordinates TSV replacement operations across all chips. This intermediary role simplifies the overall system by centralizing the complex management functions in a single controller.
Data Source
AI summary
A semiconductor apparatus may include a transmission control signal generation unit, a fuse signal transmission unit, a reception control signal generation unit and a fuse signal reception unit. The transmission control signal generation unit receives a clock signal and generates a plurality of divided clock signals based on the clock signal to output transmission control signals from the plurality of divided clock signals. The fuse signal transmission unit transmits fuse information in synchronization with the transmission control signals. The reception control signal generation unit receives the clock signal and generates the plurality of divided clock signals, and generates reception control signals based on the plurality of divided clock signals. The fuse signal reception unit receives the fuse information in synchronization with the reception control signals.