Semiconductor Interconnects with Gas-Filled Gaps
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor feature sizes decrease, the manufacturing of interconnection structures in integrated circuits faces challenges in scaling down conductive line widths and spacing while maintaining effective electrical connections and reducing parasitic capacitance, which affects device performance and integration density.
Innovation Solution
The method involves forming a semiconductor structure with gate structures, source drain structures, and conductive layers, including a stack of gate dielectric, diffusion barrier, metal, block, and wetting layers, with a gas-filled gap between conductive elements to enhance carrier mobility and reduce RC delay, using techniques like physical vapor deposition, atomic layer deposition, and chemical mechanical polishing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but parasitic capacitance increases and device performance deteriorates
Solution Approach 1:
The patent extracts the harmful dielectric material between adjacent conductive interconnects and replaces it with a gas-filled void. By removing the solid dielectric that causes parasitic capacitance and inserting gas (which has near-zero dielectric constant), the harmful capacitive coupling is eliminated while maintaining the physical structure needed for high-density integration
Solution Approach 2:
The patent changes the dielectric parameter (dielectric constant) from a high value (solid dielectric material) to near-zero (gas-filled void). This parameter change directly reduces parasitic capacitance between adjacent conductors, allowing continued scaling and density improvement without the usual capacitance penalty
2Productivity
If conductive line widths and spacing are scaled smaller to increase density, then more interconnections can be packed, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the originally continuous dielectric layer into discrete regions: solid dielectric in non-critical areas and gas-filled voids in critical high-density interconnect regions. This segmentation allows different manufacturing approaches for different areas, with the gas-filled regions providing electrical isolation that reduces sensitivity to dimensional variations
Solution Approach 2:
The gas-filled void acts as an intermediary between adjacent conductive interconnects, providing electrical isolation and reducing parasitic capacitance. This intermediary structure allows conductors to be placed closer together while maintaining electrical performance, effectively relaxing the spacing requirements
3Reliability
If gas-filled gaps are introduced to reduce parasitic capacitance, then device performance improves, but device complexity increases
Solution Approach 1:
The patent merges the void formation process with existing manufacturing steps by integrating it into the dielectric layer formation and patterning sequence. The gas-filled regions are created using modified CMP and deposition processes that combine multiple functions into unified process steps, reducing overall process complexity despite the advanced structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for improved carrier mobility, reduced parasitic capacitance, and increased integration density by optimizing the structure and process of forming conductive interconnections, thereby enhancing semiconductor device performance and reliability.
Implementation Method 1
reduced parasitic capacitance
Implementation Method 2
physical vapor deposition
Implementation Method 3
atomic layer deposition
Implementation Method 4
chemical mechanical polishing
Data Source
AI summary
A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a gate structure and a source drain structure. A recess is formed at least partially in the first dielectric layer. A protection layer is formed at least on a sidewall of the recess. The recess is deepened to expose the source drain structure. A bottom conductor is formed in the recess and is electrically connected to the source drain structure. The protection layer is removed to form a gap between the bottom conductor and the sidewall of the recess.