Semiconductor Gate Capping Liner for Short Channel Effect Suppression
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Solution Overview
Problem
Existing semiconductor devices face challenges in scaling and improving current control capabilities while effectively suppressing short channel effects.
Innovation Solution
The semiconductor device incorporates an active pattern on a substrate with multiple gate structures, epitaxial patterns, and specific gate capping patterns, including a gate capping liner and filling film, to enhance control and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi gate transistor with three-dimensional channels is used, then scaling is easily performed and current control capability is improved, but device complexity increases
Solution Approach 1:
The gate structure is divided into multiple segments (first gate electrode, second gate electrode) that are spaced apart from each other. Each gate electrode can be independently controlled, allowing for enhanced current control capability while maintaining a manageable structural complexity through modular design
Solution Approach 2:
The patent transitions from a planar gate structure to a three-dimensional multi gate structure where gate electrodes extend in directions intersecting with the active pattern. This dimensional change enables better channel control and scaling without proportionally increasing device complexity
2Productivity
If gate length is not increased, then device scaling is maintained, but current control capability may be improved through multi gate structure
Solution Approach 1:
Instead of increasing gate length in the conventional direction, the patent introduces gate electrodes that extend in directions intersecting with the active pattern at angles. This allows the gate to control the channel more effectively without increasing the traditional gate length, maintaining scaling benefits while improving control
Solution Approach 2:
The gate electrodes are positioned at specific locations spaced apart from each other, creating localized control regions. This local quality approach allows enhanced current control capability at critical points in the channel without requiring increased gate length throughout the entire device
3Object-affected harmful factors
If multi gate structure is implemented, then short channel effect is suppressed, but manufacturing precision requirements increase
Solution Approach 1:
The gate structure is segmented into multiple independent gate electrodes that can be formed using separate deposition and etching processes. This segmentation allows for better control of the short channel effect while enabling standardized manufacturing steps that reduce precision requirements
Solution Approach 2:
The patent introduces gate insulating films and gate spacers as intermediary layers between the gate electrodes and the active pattern. These intermediary structures provide buffer zones that reduce the direct impact of manufacturing variations on short channel effects, thereby suppressing the effect while reducing precision requirements
Data Source
AI summary
A semiconductor device includes an active pattern extending in a first direction on a substrate, a gate structure on the active pattern and having a gate electrode extending in a second direction intersecting the active pattern, and a gate capping pattern on the gate electrode, the gate capping pattern including a gate capping liner defining a gate capping recess, the gate capping liner having a horizontal portion along an upper surface of the gate electrode, and a vertical portion extending from the horizontal portion in a third direction intersecting the first and second directions, and a gate capping filling film on the gate capping liner and filling the gate capping recess, an epitaxial pattern on the active pattern and adjacent the gate structure, a gate contact on and connected to the gate electrode, and an active contact on and connected to the epitaxial pattern.