High-Voltage Semiconductor Gate Dielectric Structure
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Solution Overview
Problem
High-voltage semiconductor devices face a tradeoff between low on-resistance and high breakdown voltage, with traditional designs often increasing leakage when attempting to reduce the space between the drain and channel region.
Innovation Solution
A high-voltage semiconductor device with a gate dielectric structure featuring a U-shaped or ring-shaped second dielectric layer, which forms an opening exposing a first dielectric layer, allowing for a reduced space between the drain and channel region while maintaining suitable breakdown voltage, and includes a drift doping region and source/drain doping region to enhance breakdown voltage and reduce leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the space between the drain and the channel region is reduced, then the on-resistance is reduced, but the breakdown voltage is deduced and leakage is increased
Solution Approach 1:
The patent applies local quality by creating a non-uniform gate dielectric structure where the first dielectric layer has a thickness that varies in the lateral direction. Specifically, the gate dielectric structure has a greater thickness at the drain end than at the channel end, allowing different regions to have optimized properties: the channel region maintains thin dielectric for low on-resistance while the drain region has thick dielectric for high breakdown voltage and reduced leakage.
2Loss of energy
If the space between the drain and the channel region is reduced, then the on-resistance is reduced, but the leakage is increased
Solution Approach 1:
The patent applies local quality by creating a non-uniform gate dielectric structure where the first dielectric layer has a thickness that varies in the lateral direction. Specifically, the gate dielectric structure has a greater thickness at the drain end than at the channel end, allowing different regions to have optimized properties: the channel region maintains thin dielectric for low on-resistance while the drain region has thick dielectric for high breakdown voltage and reduced leakage.
3Reliability
If a non-uniform gate dielectric structure is used, then the breakdown voltage is improved, but the device complexity is increased
Solution Approach 1:
The patent applies segmentation by dividing the gate dielectric structure into multiple distinct layers: a first dielectric layer with non-uniform thickness and a second dielectric layer with uniform thickness. This segmentation allows each layer to serve a specific function - the first layer provides the non-uniform thickness profile for voltage control while the second layer provides uniform insulation, thereby managing complexity through functional division.
Solution Approach 2:
The patent applies inversion by reversing the conventional approach of using a single uniform dielectric layer. Instead of making the entire gate dielectric thin for low resistance, the invention inverts the strategy by making the dielectric thick at the drain end and thin at the channel end, achieving both low resistance and high breakdown voltage simultaneously.
Data Source
AI summary
A high-voltage semiconductor device is provided. The device includes a semiconductor substrate including a high-voltage well region. The device further includes a gate dielectric structure and a gate. The gate dielectric structure includes a first dielectric layer over the high-voltage well region and a second dielectric layer over the first dielectric layer. The second dielectric layer has a U-shaped or ring-shaped contour as viewed from a top-view aspect, so as to form an opening exposing the first dielectric layer. The gate is disposed over the second dielectric layer and extends onto the exposed first dielectric layer via the opening. The device further includes a drift doping region in the high-voltage well region and a source/drain doping region in the drift doping region. A method for fabricating the high-voltage semiconductor device is also provided.


