Semiconductor Gate Dielectric Leakage Current Reduction
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Solution Overview
Problem
The challenge in semiconductor manufacturing is the large leakage current issue in shrinking semiconductor devices, particularly due to the limitations of traditional silicon oxide gate dielectric layers, which affects the electrical properties and reliability of MOSFETs, and is exacerbated by the difficulty in forming high-quality interlayer dielectric layers and activating doping ions without excessive diffusion.
Innovation Solution
A method involving a substrate with dummy gate structures, thermal annealing processes to increase interlayer dielectric layer density and activate doping ions, and a high-K metal gate structure with an interface layer and sidewall spacers, where the first thermal annealing process activates doping ions and the second process further densifies the gate dielectric layer without excessive ion diffusion, reducing thermal budget and improving electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional silicon oxide gate dielectric layer is used, then manufacturing process is simple, but leakage current increases due to continuous thickness shrinking
Solution Approach 1:
The patent changes the dielectric constant parameter by replacing silicon oxide with high-K dielectric material (such as HfO2, Al2O3, or TiO2), which has a higher dielectric constant than traditional silicon oxide. This allows achieving the same capacitive effect with greater thickness, thereby reducing leakage current while maintaining electrical performance
Solution Approach 2:
The patent employs a composite gate dielectric structure consisting of multiple layers including high-K dielectric material layers combined with interface layers. This composite structure optimizes both electrical performance (reducing leakage) and manufacturing compatibility
2Reliability
If thermal annealing process is performed to activate doping ions, then doping ion activation improves, but excessive diffusion of doping ions occurs
Solution Approach 1:
The patent employs a multi-stage thermal annealing process with different temperature conditions and durations. The first annealing process activates doping ions at controlled conditions, while subsequent annealing processes are optimized for specific objectives, preventing excessive diffusion while ensuring complete activation
Solution Approach 2:
The patent performs thermal annealing processes at strategically timed stages: first before removing dummy gate structures to activate doping ions in the substrate, and second after removing dummy gates to further activate ions and densify the gate dielectric layer. This preliminary and staged approach ensures optimal activation without excessive diffusion
3Reliability
If interlayer dielectric layer density is increased through thermal annealing, then layer reliability improves, but thermal budget increases
Solution Approach 1:
The patent combines multiple objectives into unified thermal annealing processes: the first annealing process simultaneously activates doping ions in the substrate and begins densifying the interlayer dielectric layer, while the second annealing process completes both activation and densification. This merging reduces the total number of separate thermal processes and optimizes thermal budget usage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces leakage current, enhances the density and reliability of interlayer and gate dielectric layers, and improves the activation of doping ions, leading to improved electrical properties and reduced thermal budget in semiconductor devices.
Implementation Method 1
performing a first step thermal annealing process onto the interlayer dielectric layer and the doping regions to increase the density of the interlayer dielectric layer and activate doping ions
Implementation Method 2
activate doping ions in the doping regions without causing an excess diffusion of the doping ions in the doping region
Implementation Method 3
performing a second step thermal annealing process onto the gate dielectric layer and the doping regions to activate the doping ions in the doping regions for a second time and increase the density of the density of the gate dielectric layer
Data Source
AI summary
A method for fabricating a semiconductor device includes providing a substrate; and forming at least one dummy gate structure on the substrate. The method also includes forming doping regions in the substrate at both sides of the dummy gate structure; forming an interlayer dielectric layer on the d the dummy gate structure; performing a first step thermal annealing process to increase a density of the interlayer dielectric layer; and activating doping ions for a first time without an excess diffusion of the doping ions in the doping region; and removing the dummy gate structure to expose the surface of the substrate to form a trench in the annealed interlayer dielectric layer. Further, the method also includes forming a gate dielectric layer on the surface of the substrate on bottom of the trench; and performing a second step thermal annealing process to activate the doping ions for a second time.