Semiconductor Device Gate Electrode Length Control
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Solution Overview
Problem
The existing semiconductor device manufacturing method results in a low-voltage transistor with a gate electrode of insufficient length due to a top surface of the device separating area being significantly lower than the active region, leading to undesirable electrical characteristics.
Innovation Solution
The method involves forming a semiconductor device with distinct transistor regions having varying gate insulating film thicknesses, ensuring the top surface of the device separating area in the low-voltage transistor region is equal to or higher than the active region, preventing excessive thinning of the photoresist pattern for the gate electrode, thus allowing for the formation of a transistor with a desired gate length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If transistors with different gate insulating film thicknesses are formed in different regions, then electrical characteristics are improved, but the top surface height of device separating areas becomes uneven across regions
Solution Approach 1:
The patent applies local quality by forming device separating areas with different heights in different transistor regions. Specifically, the low-voltage transistor region has a higher device separating area top surface compared to high-voltage and intermediate-voltage transistor regions. This localized height adjustment ensures that the photoresist pattern maintains sufficient thickness during gate electrode formation in the low-voltage region, enabling precise gate length control and desirable electrical characteristics for each transistor type.
2Ease of manufacture
If device separating area top surface is lower than active region, then manufacturing is simplified, but photoresist pattern becomes excessively thin, preventing formation of gate electrode with desired length
Solution Approach 1:
The patent implements local quality by creating region-specific device separating area heights. In the low-voltage transistor forming region, the device separating area top surface is positioned at a higher level (closer to or equal with the active region top surface) to prevent photoresist pattern thinning. This localized adjustment ensures sufficient photoresist thickness for accurate gate electrode patterning, while other regions can maintain simpler structures.
Solution Approach 2:
The patent applies preliminary action by pre-adjusting the device separating area height in the low-voltage transistor region before forming the gate electrode. The device separating area is formed to protrude or be level with the active region surface in advance, creating a favorable topography that prevents subsequent photoresist pattern thinning during gate electrode formation, thus ensuring manufacturing precision.
3Reliability
If device separating area top surface is significantly lower than active region, then device isolation is improved, but gate electrode length control becomes impossible
Solution Approach 1:
The patent applies local quality by differentiating device separating area heights across different transistor regions. The low-voltage transistor region features a higher device separating area that prevents photoresist thinning, enabling precise gate length formation. Other voltage regions maintain lower device separating areas for adequate isolation, thus achieving both isolation and precision requirements locally.
Solution Approach 2:
The patent utilizes the vertical dimension (height) of the device separating area to solve the problem. By adjusting the height of device separating areas in specific regions, the patent creates a three-dimensional topography that prevents photoresist pattern thinning during gate electrode formation, thereby enabling precise gate length control without compromising device isolation.
Data Source
AI summary
A method of manufacturing a semiconductor device comprises forming a first insulator in the first area of a substrate and a second insulator formed in a second area of the substrate; forming an etching preventing film extending over the first device region surrounded by the first area and the second device region surrounded by the second area removing the etching preventing film from the first device region and first area forming a first gate insulating film over the first device region while the second device region and the second area are covered by the etching preventing film; removing the etching preventing film over the second device region and the second area forming a second gate insulating film over the second device region; and forming a first gate electrode on the first gate insulating film and forming a second gate electrode on the second gate insulating film.