Semiconductor Cell Layout With Gate-Fin Overlap for Higher Density
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Solution Overview
Problem
Existing design rules for semiconductor devices result in wasted space due to restrictions on gate patterns not overlapping straddling fin patterns, leading to reduced cell density and inefficient use of layout diagrams.
Innovation Solution
Allowing gate patterns to overlap and electrically couple with straddling fin patterns, resulting in a ⅖ reduction in height and improved cell density by eliminating unnecessary space in semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate patterns are restricted from overlapping straddling fin patterns, then manufacturing reliability is improved, but cell density deteriorates
Solution Approach 1:
The patent divides the straddling fin pattern into multiple segments by introducing discontinuities or gaps. This segmentation allows gate patterns to be positioned in the spaces between fin segments, enabling overlap while maintaining manufacturing reliability through controlled separation of critical regions.
Solution Approach 2:
The patent resolves the two-dimensional layout conflict by introducing a third dimension through multi-layer metallization and via structures. Gate patterns can overlap fin patterns in the planar view while being separated in the vertical dimension through different metal layers and interconnect structures, thus achieving both high density and manufacturing reliability.
2Quantity of substance
If gate patterns overlap straddling fin patterns, then cell density is improved, but manufacturing precision deteriorates
Solution Approach 1:
The patent introduces intermediary structures such as mandrels, spacers, and via holes that mediate between the gate patterns and straddling fin patterns. These intermediaries provide controlled coupling paths and isolation regions, enabling precise alignment and electrical connection while maintaining manufacturing feasibility through standardized process steps.
Solution Approach 2:
The patent employs preliminary patterning steps where mandrels and spacers are formed before the final gate and fin structures. This preliminary action establishes precise geometric relationships and alignment references that guide subsequent processing steps, ensuring that overlapping patterns are formed with the required precision through a sequence of controlled operations.
Data Source
AI summary
A semiconductor device includes: first fins (F-fins) and second fins (S-fin) arranged in a first row having a single-row height and that includes an alpha cell region and a beta cell region. The alpha cell region includes a first F-fin, a first S-fin and a first gate structure overlapping each of the first F-fin and the first S-fin. The first gate structure does not overlap top and bottom edges of the alpha cell region. The beta cell region includes second and third F-fins, second and third S-fins and a second gate structure overlapping each of the second F-fin and second S-fin and at least one of the third F-fin or the third S-fin. A top edge of the beta cell region being co-track aligned with the third F-fin. A bottom edge of the beta cell region being co-track aligned with the third S-fin.