Semiconductor Device Manufacturing with Segmented Gate Insulating Films

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Solution Overview

Problem

Conventional methods for manufacturing semiconductor devices with both trench-gate and planar transistors on the same substrate require multiple thermal oxidation steps, leading to increased oxidation stress and degradation of DRAM refresh characteristics due to the need for simultaneous formation of thick and thin gate insulating films.

Innovation Solution

A method where a first gate insulating film is formed in the peripheral circuit region, covered with a protective film, and a second thicker gate insulating film is formed independently within the gate trench of the memory cell region, reducing the number of oxidation steps and allowing independent control of film thickness and characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple thermal oxidation steps are performed to form both thick and thin gate insulating films simultaneously, then both trench-gate and planar transistors can be formed on the same substrate, but oxidation stress increases and DRAM refresh characteristics deteriorate

Engineering Contradiction:
Improveability to form both trench-gate and planar transistorsVSAvoidDRAM refresh characteristics
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The gate insulating film formation process is segmented into separate steps: first forming a thin gate insulating film in the peripheral circuit region, then forming a thick gate insulating film only in the memory cell region gate trench. This segmentation allows each region to have its required film thickness without subjecting the entire substrate to multiple thermal oxidation cycles, thereby reducing oxidation stress while maintaining the ability to form both transistor types.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different gate insulating film thicknesses are applied to different regions based on their specific requirements: the peripheral circuit region receives a thin gate insulating film for low-voltage operation, while the memory cell region receives a thick gate insulating film for high breakdown voltage. This local differentiation eliminates the need for simultaneous formation of both thicknesses through multiple thermal oxidation steps.

Inventive Principle:
Principle #3Local quality

2Strength

If a thick gate insulating film is formed in the memory cell region through multiple oxidation steps, then high breakdown voltage is achieved, but the number of thermal oxidation steps increases and oxidation stress accumulates

Engineering Contradiction:
Improvebreakdown voltageVSAvoidnumber of thermal oxidation steps
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

A thin gate insulating film is formed preliminarily across the entire substrate including the memory cell region before gate trench formation. Subsequently, the gate trench is etched and a thick gate insulating film is formed only within the trench. This preliminary action eliminates the need for multiple thermal oxidation steps to achieve the thick film, as the thick film is formed in a single step after trench formation, reducing oxidation stress while maintaining high breakdown voltage.

Inventive Principle:
Principle #10Preliminary action

3Use of energy by moving object

If a thin gate insulating film is formed in the peripheral circuit region, then low-voltage operation is enabled, but forming both thick and thin films simultaneously requires complex multi-step oxidation processes

Engineering Contradiction:
Improveoperating voltageVSAvoidoxidation process steps
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The substrate is divided into memory cell region and peripheral circuit region, with each region receiving appropriate gate insulating film thickness through separate formation steps. The peripheral circuit region is processed first to receive a thin gate insulating film for low-voltage operation, while the memory cell region is subsequently processed to receive a thick gate insulating film. This segmentation eliminates the need for complex simultaneous formation processes.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The thin gate insulating film is formed preliminarily in the peripheral circuit region before any processing of the memory cell region. This preliminary formation of the thin film allows the peripheral circuit to achieve low-voltage operation while the subsequent independent processing of the memory cell region allows for thick film formation without requiring complex simultaneous multi-step oxidation processes.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces oxidation stress and prevents degradation of DRAM refresh characteristics, enabling high-performance formation of both trench-gate transistors with thick gate insulating films and planar transistors with thin gate insulating films on the same substrate.

Implementation Method 1

a protective film is formed to cover the first gate insulating film

Methodology Applied
Scientific EffectPhysical barrier protection:

Implementation Method 2

a second gate insulating film that is thicker than the first gate insulating film is formed independently within the gate trench of the memory cell region

Methodology Applied
Scientific EffectThermal oxidation: Oxidation

Data Source

PatentUS7935595B2Method for manufacturing semiconductor device
Publication Date: 2011.05.03 MICRON TECHNOLOGY INC
  • US7935595B2 patent drawing
  • US7935595B2 patent drawing
  • US7935595B2 patent drawing

AI summary

A method for manufacturing a semiconductor device whereby the process is simplified and high performance can be obtained in both a trench-gate transistor and a planar transistor that has a thin gate insulating film when the two transistors are formed on the same semiconductor substrate. In a state in which the gate insulating film (11s) in a peripheral circuit region PE is covered by a protective film (12), a gate trench (18) is formed in a memory cell region M, after which a gate insulating film (19) that is thicker than the gate insulating film (11s) is formed on an inner wall of the gate trench (18) in a state in which the gate insulating film (11s) of the peripheral circuit region PE is still covered by the protective film (12).