Semiconductor Integrated Circuit Gate Line Segmentation
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Solution Overview
Problem
Semiconductor integrated circuits face variations in transistor dimensions and increased circuit area due to arbitrary separation of gate lines and the need for additional metal layers, leading to reduced yields and increased chip size.
Innovation Solution
A semiconductor integrated circuit design featuring PMOS and NMOS transistors aligned in specific directions with linearly extending gate lines that pass through their gate areas, reducing variations in dimensions and eliminating the need for arbitrary gate line separation, thereby minimizing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If gate lines are separated into segments at arbitrary locations to avoid coherent light effects, then the effect of diffracted light is reduced, but variations in gate line width occur at adjacent locations and degree of freedom is reduced
Solution Approach 1:
The gate line is divided into multiple segments (first gate line segment and second gate line segment) that are separated in the first direction. This segmentation allows each segment to be independently positioned and sized, enabling the avoidance of coherent light effects at critical locations while maintaining controlled dimensions at other locations. The segments can be spaced apart to reduce diffraction effects without causing width variations at adjacent locations.
Solution Approach 2:
The invention transitions from arbitrary point-based separation to structured multi-dimensional arrangement. Gate line segments are arranged in specific patterns involving multiple directions (first direction for separation, second direction for alignment). This dimensional approach allows coherent light effects to be avoided while maintaining uniform width through controlled geometric relationships between segments.
2Adaptability or versatility
If two metal layers are used to complement wiring resources, then circuit function is achieved, but cell height increases and contact failure risk increases
Solution Approach 1:
The gate lines are designed to serve multiple functions simultaneously. The segmented gate line structure provides both transistor gating functionality and wiring resource functionality. By arranging segments in specific patterns, the gate lines can complement each other as wiring resources without requiring additional dedicated metal layers, thereby maintaining reliability while achieving circuit functions.
Solution Approach 2:
The invention merges the gating function and wiring function into a single structural element (the segmented gate line). Instead of using separate metal layers for wiring complement, the gate line segments themselves are positioned and configured to provide additional wiring resources, eliminating the need for extra metal layers and associated contact structures.
3Object-affected harmful factors
If gate lines are separated into segments, then coherent light effects are avoided, but circuit area is affected
Solution Approach 1:
The gate line segments are arranged with different characteristics in different locations. In regions where coherent light effects are problematic, segments are separated or positioned to avoid these effects. In other regions, segments are arranged to minimize area occupation. This local optimization allows diffracted light effects to be avoided while keeping the overall circuit area minimal.
Data Source
AI summary
A plurality of PMOS transistors are provided on a substrate along an X-axis direction such that a gate length direction of each of the PMOS transistors is parallel to the X-axis direction. A plurality of NMOS transistors are provided on the substrate along the X-axis direction such that a gate length direction of each of the NMOS transistors is parallel to the X-axis direction, and each of the plurality of NMOS transistors is opposed to a corresponding one of the PMOS transistors in the Y-axis direction. Gate lines respectively correspond to the PMOS transistors and the NMOS transistors, and are arranged parallel to each other and extend linearly along the Y-axis direction such that each of the gate lines passes through gate areas of the PMOS transistors and NMOS transistors which correspond to each of the gate lines.