Semiconductor Device Gate Electrode Segmentation for Switching Loss Reduction

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Solution Overview

Problem

Semiconductor devices, such as MOSFETs and IGBTs, face challenges in minimizing switching loss due to high reverse transfer capacitance, which affects their efficiency and switching times.

Innovation Solution

The semiconductor device design includes a gate electrode with multiple portions, where the second portion is positioned higher than the p-n junction surface, reducing capacitance between the gate and drain electrodes, and incorporating a conductive portion to further minimize capacitance, thereby reducing switching loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If the gate electrode is positioned closer to the drain electrode to improve control, then the control efficiency is improved, but the reverse transfer capacitance increases leading to higher switching loss

Engineering Contradiction:
Improvecontrol efficiencyVSAvoidswitching loss
Core Design Contradiction:
Ease of operationVSLoss of energy

Solution Approach 1:

The gate electrode is divided into two distinct portions: a first portion that opposes the third semiconductor region (drain) and a second portion that opposes the second semiconductor region (channel). This segmentation allows the gate to fulfill multiple functions - the first portion provides control over the channel while the second portion minimizes capacitive coupling with the drain, thereby reducing reverse transfer capacitance and switching loss while maintaining control efficiency.

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If the gate electrode structure is simplified to reduce manufacturing complexity, then the manufacturing process is easier, but the capacitance reduction effect is compromised

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidswitching loss
Core Design Contradiction:
Ease of manufactureVSLoss of energy

Solution Approach 1:

The gate electrode structure utilizes vertical positioning differences in addition to horizontal arrangement. The second portion of the gate electrode is positioned higher than the interface between the first and second semiconductor regions, creating a three-dimensional configuration. This dimensional approach reduces capacitive overlap with the drain region while maintaining a relatively simple planar manufacturing process, balancing manufacturing ease with effective capacitance reduction.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively reduces switching loss by minimizing capacitance, leading to shorter rise and fall times and more uniform current flow, enhancing the device's efficiency and reliability.

Implementation Method 1

The first portion opposes the third semiconductor region, the second semiconductor region, and a portion of the first semiconductor region in a first direction with a gate insulating portion interposed

Methodology Applied
Scientific EffectElectric Field: Electric Field

Data Source

PatentUS10872975B2Semiconductor device
Publication Date: 2020.12.22 KK TOSHIBA
  • US10872975B2 patent drawing
  • US10872975B2 patent drawing
  • US10872975B2 patent drawing

AI summary

According to an embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, and a second electrode. The gate electrode includes a first portion and a second portion. The first portion opposes the third semiconductor region, the second semiconductor region, and a portion of the first semiconductor region in a first direction perpendicular to a second direction from the first electrode toward the first semiconductor region. The second portion is arranged with the first portion in a third direction perpendicular to the first and first directions. The second portion opposes the second semiconductor region in the first direction. A lower end of the second portion is positioned higher than an interface between the first semiconductor region and the second semiconductor region.