Semiconductor Gate Structure with Segmented Conductive Word Lines
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Solution Overview
Problem
The integration of semiconductor memory is limited by the array structure, leading to reduced memory size and insufficient current in memory cells due to the short channel effect and the inability to implant dopants between adjacent word lines as the interval between them is reduced.
Innovation Solution
A gate structure with a conductive word line structure that includes a middle portion and spacer portions with increasing width, allowing for enhanced integration by eliminating the need for dopant implantation and increasing the current of memory cells through the formation of an inversion area between adjacent word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the interval between adjacent word lines is reduced to increase integration, then the memory size is reduced and integration is increased, but dopant implantation becomes impossible and the current of memory cells becomes insufficient
Solution Approach 1:
The conductive word line structure is segmented into a middle portion and two spacer portions. The middle portion has a first width and the spacer portions have a second width that is greater than the first width. This segmentation allows the word line to have different widths in different regions, enabling increased current through the wider spacer portions while maintaining compact integration through the narrower middle portion.
Solution Approach 2:
Different portions of the conductive word line structure are given different local qualities (widths). The spacer portions have a larger width to increase current, while the middle portion has a smaller width to save space. This local differentiation resolves the contradiction between integration and current by optimizing each region for its specific function.
2Reliability
If the width of conductive structure is increased to increase memory cell current, then reading/writing speed is improved, but the interval between adjacent word lines must be increased
Solution Approach 1:
The conductive word line structure is divided into a middle portion and two spacer portions with different widths. The spacer portions have greater width to increase current, while the middle portion has lesser width to minimize the interval between adjacent word lines. This segmentation allows simultaneous optimization of current and integration.
Solution Approach 2:
The word line structure employs local quality variation where spacer portions have increased width for current enhancement while the middle portion maintains reduced width for compact spacing. This resolves the contradiction by applying different width characteristics to different functional regions of the same structure.
3Reliability
If dopant implantation is performed between adjacent word lines to form drain or source, then memory cell function is achieved, but the apparatus limitation prevents implantation when interval is reduced
Solution Approach 1:
The invention extracts the dopant implantation step from the manufacturing process by using an inversion area that forms naturally between adjacent word lines with different potentials. This eliminates the need for dopant implantation apparatus and simplifies the manufacturing process while maintaining memory cell function.
Solution Approach 2:
The inversion area acts as an intermediary between adjacent word lines, serving the function previously provided by doped drain or source regions. This inversion area forms due to the electric field between word lines with different potentials, eliminating the need for physical dopant implantation.
Data Source
AI summary
A gate structure for a semiconductor device is provided. The gate structure includes a conductive structure. The conductive structure insulatively disposed over a substrate includes a middle portion and two spacer portions. The middle portion has a first surface and two second surfaces. The first surface is between the two second surfaces. The two spacer portions are respectively connected to the two second surfaces of the middle portion. A width of each of the two spacer portions gradually increases from top to bottom.