Semiconductor Gate Shunting Wiring for Power MOS Transistors
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Solution Overview
Problem
Power MOS transistors face a tradeoff between low on-resistance and high switching performance, with increasing impurity concentration in the drift layer reducing drain-source breakdown voltage, and existing methods to decrease gate resistance, such as using tungsten plug electrodes, limit miniaturization and further performance enhancement.
Innovation Solution
The semiconductor device incorporates a gate shunting substrate wiring made of copper with large thickness and low resistance, connected to the gate electrode through protrusion electrodes, which reduces the gate resistance and enhances switching performance by distributing the gate potential evenly across the transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate width is increased to decrease on-resistance, then the on-resistance decreases, but the die size increases
Solution Approach 1:
The drift layer is segmented into multiple regions with different impurity concentrations along the gate width direction. This allows the effective conduction area to be increased through optimized current distribution in high-concentration regions while maintaining compact overall device dimensions, thus reducing on-resistance without proportionally increasing die size.
2Speed
If the gate resistance is decreased to improve switching performance, then the switching performance improves, but the device complexity increases
Solution Approach 1:
A low-resistance conductive layer is introduced as an intermediary between the gate electrode and the channel region. This intermediate layer provides a low-impedance path for gate signal distribution, significantly reducing gate resistance and improving switching speed without requiring complex multi-layer gate structures or additional control circuits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly decreases the rise and fall times of the gate voltage, improving the switching performance of the power MOS transistor while allowing for smaller wiring patterns and maintaining low on-resistance.
Implementation Method 1
a gate shunting substrate wiring, both ends of which are connected to the gate electrode... made of copper with large thickness and low resistance... reduces the gate resistance
Data Source
AI summary
In one embodiment, a semiconductor chip includes a gate electrode extending between a source electrode and a drain electrode. The source electrode and the drain electrode include finger form electrodes that are an engaged arrangement with each other. One or more gate drawing electrodes are connected to portions of the gate electrode, and protrusion electrodes connect the gate drawing electrodes to a gate shunting wiring disposed on a substrate.