Semiconductor Gate Structure Sidewall Self-Assembly Material
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Solution Overview
Problem
The application of high-K dielectric materials in semiconductor manufacturing leads to increased parasitic capacitance and coverage issues with metal deposition, particularly in gate-last processes, resulting in voids and short circuits due to the complexity of sophisticated manufacturing processes required.
Innovation Solution
A semiconductor device with sidewalls formed of a self-assembly material, such as CH3(CH2)xCH2SiCl3, is used to reduce the dielectric constant of the sidewalls and improve metal film coverage, where the self-assembly material is interposed between the metal gate and spacers, and a conductive buffer layer is introduced between the gate dielectric and metal gate to enhance adhesion and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If high-K dielectric materials are used to form sidewalls, then device dimensions can be reduced, but parasitic capacitance increases
Solution Approach 1:
The patent removes the high-K dielectric sidewalls entirely and replaces them with low-K dielectric materials, extracting the harmful parasitic capacitance effect while maintaining the device's dimensional scaling benefits
Solution Approach 2:
The patent changes the dielectric constant parameter of the sidewall material from high-K to low-K, fundamentally altering the electrical properties to reduce parasitic capacitance while preserving the geometric dimensions needed for device scaling
2Length of moving object
If high-K dielectric materials are used for gate dielectric layer, then device dimensions can be reduced, but metal film coverage deteriorates causing voids and short circuits
Solution Approach 1:
The patent introduces a conductive buffer layer as an intermediary between the gate dielectric and metal gate, which improves adhesion and enables complete metal film coverage, eliminating voids and short circuits
Solution Approach 2:
The conductive buffer layer is deposited in advance before the metal gate formation, preparing the surface with proper adhesion properties that enable subsequent complete metal coverage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance and improves metal film coverage by lowering the dielectric constant of the sidewalls and eliminating high-K dielectric sidewalls, thereby enhancing the yield and simplifying the manufacturing process in semiconductor devices.
Implementation Method 1
sidewalls are formed of a self-assembly material
Implementation Method 2
reduce the K value (i.e., dielectric constant) of a dielectric material for forming the sidewalls
Implementation Method 3
a conductive buffer layer is introduced between the gate dielectric and metal gate to enhance adhesion
Data Source
AI summary
A semiconductor device includes a substrate having an active region, a gate structure on the active region, and spacers formed on opposite sides of the gate structure. The gate structure includes a gate dielectric layer on the active region, a metal gate on the gate dielectric layer, and sidewalls on both side surfaces of the gate structure. Each of the sidewalls is interposed between the metal gate and one of the spacers. The sidewalls include a self-assembly material. The gate dielectric layer includes a high-K material. The spacers include silicon nitride. The gate structure also includes a buffer layer interposed between the metal gate and the gate dielectric layer.