Semiconductor Gate Electrode Silicidation and Planarization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing manufacturing processes for nonvolatile semiconductor memory devices face challenges in achieving high selectivity between the barrier layer and the interlayer insulating layer, leading to variations in interconnect resistance and difficulties in forming contact plugs due to differences in etch rates and material combinations.
Innovation Solution
A semiconductor device design featuring a semiconductor substrate with silicided gate electrodes and non-silicided high-resistivity gate structures, where a first interlayer insulating layer is formed between the gate electrodes, and a second interlayer insulating layer is deposited to planarize the surface, allowing for the formation of electrically insulated interconnect layers and contact plugs that connect with source/drain areas.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the barrier layer is formed to coat the gate electrodes and gate structures, then the gate electrodes are protected and silicidation is enabled, but the interlayer insulating layer is etched partially due to insufficient selectivity
Solution Approach 1:
A planarization layer is introduced as an intermediary between the barrier layer and the interlayer insulating layer. This planarization layer serves as a protective mediator that prevents the etching of the interlayer insulating layer while allowing the barrier layer to perform its protective function on the gate electrodes.
Solution Approach 2:
The insulating layer structure is segmented into multiple distinct layers: the original interlayer insulating layer, a newly added planarization layer, and the barrier layer. This segmentation allows each layer to perform its specific function independently, with the planarization layer specifically tasked with preventing unwanted etching.
2Manufacturing precision
If high selectivity between barrier layer and interlayer insulating layer is attempted, then etching of interlayer insulating layer is prevented, but no suitable material combination has been realized
Solution Approach 1:
The planarization layer acts as an intermediary that decouples the selectivity requirement from the material combination constraints. By introducing this intermediate layer, the system achieves the desired etching protection without requiring an ideal material combination between the barrier layer and interlayer insulating layer.
Solution Approach 2:
The planarization layer is designed to be self-etching or selectively removable in subsequent processing steps. This self-service characteristic allows the layer to perform its protective function during critical steps while being easily removed or modified later without requiring complex material combinations.
3Ease of manufacture
If the interlayer insulating layer top becomes lower than gate electrode top, then barrier layer formation is enabled, but depressions are formed in subsequent interlayer insulating layer causing interconnect resistance variations
Solution Approach 1:
The planarization layer is formed in advance to fill and compensate for the depressions created by the stepped topology. This preliminary action ensures that the surface is sufficiently planar before subsequent interconnect formation, preventing resistance variations while maintaining the stepped structure needed for barrier layer formation.
Solution Approach 2:
The solution addresses the surface topology problem by adding a vertical dimension through the planarization layer. Instead of trying to flatten the horizontal surface, the planarization layer provides vertical compensation, filling depressions and creating a planar surface for subsequent processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents the etching of the interlayer insulating layer, maintains the integrity of the interconnect layers, and ensures consistent contact plug formation, thereby reducing variations in interconnect resistance and improving manufacturing efficiency.
Implementation Method 1
The gate electrodes of the cell transistors and select gate transistors may be subjected to silicidation. The silicidation of the gate electrodes can lower the resistance between them and contact plugs.
Implementation Method 2
The gate structure which is not subjected to silicidation is coated with a barrier layer.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate having a first surface. First gate electrodes are formed along a first direction on the first surface. Source/drain areas are formed in the first surface and sandwich a channel region. A first interlayer insulating layer fills a region between the first gate electrodes and has the top lower than the tops of the first gate electrodes. A second interlayer insulating layer is formed above the first gate electrodes and the first interlayer insulating layer. Interconnect layers are formed in the second interlayer insulating layer along a direction which intersects the first direction and is insulated from each other. A region between the interconnect layers is filled with the second interlayer insulating layer. A contact plug is formed in the first and second interlayer insulating layers and is in contact with the interconnect layer and the source/drain area.