Semiconductor Gate Spacing for Optical Proximity Effect Control
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Solution Overview
Problem
The optical proximity effect in semiconductor integrated circuits leads to significant dispersion of gate length due to varying gate lengths and intervals, making it difficult to achieve high performance and flexibility in design, as conventional correction techniques either delay processing or degrade circuit characteristics.
Innovation Solution
By setting a wider space between transistors and adjacent gates, or using spacer standard cells with no active transistors, the semiconductor integrated circuit design limits the influence of neighboring gate patterns, thereby suppressing dispersion of gate length and maintaining design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate length and gate intervals are equalized to single values for layout, then dispersion of gate length is suppressed, but flexibility of design is lowered
Solution Approach 1:
The patent applies local quality by making the space between gates adjacent to active transistors specifically larger than other spaces, rather than uniformly equalizing all gate intervals. This localized adjustment suppresses optical proximity effect where it matters most while preserving design flexibility elsewhere in the circuit.
Solution Approach 2:
The patent changes the spatial parameter (gate interval) selectively based on the functional state of adjacent transistors. By adjusting the space between gates according to whether adjacent transistors are active or not, the patent achieves both gate length consistency and design flexibility through dynamic parameter adaptation.
2Manufacturing precision
If OPC (Optical Proximity Correction) is performed to correct gate mask, then dimensional error is reduced, but processing time and complexity increase
Solution Approach 1:
The patent performs preliminary action by pre-adjusting the space between gates during the layout design phase, before photolithography and exposure. By proactively designing larger spaces between gates adjacent to active transistors, the patent prevents optical proximity effect from causing dimensional errors, eliminating the need for time-consuming OPC processing.
Solution Approach 2:
The patent extracts and addresses the root cause of optical proximity effect (inappropriate gate spacing) separately from the general layout design process. By isolating and pre-correcting the spacing parameter, the patent removes the need for subsequent complex OPC processing while maintaining dimensional accuracy.
3Speed
If gate length is reduced for transistor miniaturization, then circuit performance improves, but influence of optical proximity effect increases
Solution Approach 1:
The patent applies preliminary anti-action by pre-compensating for the optical proximity effect through larger gate spacing before the harmful effect can occur during photolithography. By anticipating and counteracting the dimensional expansion caused by diffracted light, the patent maintains precise gate length control even as transistor dimensions are reduced for improved performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the optical proximity effect's impact on gate length dispersion, allowing for consistent and precise gate dimensions, even with arbitrary gate lengths and intervals, thereby enhancing the performance and flexibility of semiconductor integrated circuits.
Implementation Method 1
when the pattern dimension is smaller than the wavelength of exposure light, optical proximity effect by an influence of diffracted light makes error between a layout dimension at design and an actual pattern dimension in the semiconductor substrate large
Data Source
AI summary
A semiconductor integrated circuit includes a first transistor which is formed of a first gate extending in a first direction and a first diffusion region and which is capable of being active, a second transistor which is formed of a second gate extending in the first direction and a second diffusion region and which is arranged adjacent to the first transistor in a second direction intersected at a right angle with the first direction, and a third gate which extends in the first direction and which is arranged adjacent in the second direction to the first transistor on an opposite side to the second transistor. A space between the first gate and the second gate is larger than a space between the first gate and the third gate.