3D Semiconductor Memory Gate-Stack Through Regions
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Solution Overview
Problem
Current three-dimensional semiconductor memory devices face challenges in integrating a large number of gate electrodes while maintaining effective electrical connections to peripheral circuits, leading to increased defects and reduced integration efficiency.
Innovation Solution
The proposed solution involves a gate-stack structure with through regions penetrating through the gate-stack structure, surrounded by word lines and select lines, and vertical channel structures, allowing for shared word lines between memory cell array regions and enhanced electrical connections via step-shaped contact regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the amount of stacked gate electrodes is increased to achieve high integration, then integration density is improved, but manufacturing complexity and defect rate increase
Solution Approach 1:
The gate-stack structure is divided into multiple segments with through regions penetrating through at different positions. This segmentation allows independent formation and connection of vertical channel structures in different regions, reducing manufacturing complexity while maintaining high integration density through parallel processing of multiple segments
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacking by forming gate electrodes in vertical layers. Multiple gate electrodes are stacked in the vertical direction (perpendicular to substrate) with through regions providing access from top and bottom surfaces, enabling high integration density without proportionally increasing lateral manufacturing complexity
2Quantity of substance
If more gate electrodes are stacked to improve integration, then storage capacity increases, but electrical connection reliability to peripheral circuits deteriorates
Solution Approach 1:
The structure is divided into memory cell array regions separated by through regions. This segmentation allows peripheral circuits to be positioned in through regions with direct vertical access to gate electrodes, ensuring reliable electrical connections while maintaining high storage capacity in the memory cell regions
Solution Approach 2:
Through regions act as intermediary zones between peripheral circuits and the stacked gate electrodes. These regions provide dedicated pathways for electrical connections, mediating between the high-density memory cell arrays and peripheral circuitry to ensure signal integrity and connection reliability
3Quantity of substance
If gate electrodes are densely stacked to increase integration, then device miniaturization is achieved, but defect rate increases
Solution Approach 1:
The gate-stack structure is divided into multiple segments separated by through regions. This segmentation isolates potential defects to specific segments, preventing defect propagation across the entire structure. Each segment can be independently formed and tested, reducing overall defect rate while maintaining high integration density
Solution Approach 2:
Through regions are incorporated into the structure beforehand as isolation zones and stress relief features. These regions cushion against defect propagation and provide buffer zones that prevent manufacturing variations in one area from affecting adjacent areas, thereby reducing overall defect rate in high-density structures
Data Source
AI summary
A three-dimensional semiconductor memory device including a gate-stack structure on a base substrate, the gate-stack structure including gate electrodes stacked in a direction perpendicular to a surface of the base substrate and spaced apart from each other; a through region penetrating through the gate-stack structure and surrounded by the gate-stack structure; and first vertical channel structures and second vertical channel structures on both sides of the through region and penetrating through the gate-stack structure, wherein the through region is between the first vertical channel structures and the second vertical channel structures.