Semiconductor Gate Wiring Layout for Lower Contact Resistance

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Solution Overview

Problem

In semiconductor devices, the total resistance of gate and source/drain structures, contact plugs, and via structures increases due to contact resistance, and electrical shorts can occur between these components, affecting device performance.

Innovation Solution

The semiconductor device design includes specific gate and source/drain structures with contact plugs and insulation patterns, where the upper surface of the second contact plug is lower than the first, reducing total contact resistance and preventing electrical shorts by eliminating the need for contact plugs or vias between certain components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If contact plugs and via structures are formed to connect gate structure and source/drain layer to upper wirings, then electrical connection is established, but total resistance increases due to contact resistance

Engineering Contradiction:
Improveelectrical connectionVSAvoidtotal resistance
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent removes the contact plug structure from between the gate electrode and the upper wiring. Instead, the upper wiring directly contacts the gate electrode, eliminating the contact resistance that would occur at the gate electrode-contact plug interface. This extraction of the unnecessary contact plug component directly reduces total resistance while maintaining electrical connection.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

Conventionally, the structure is designed with contact plugs to elevate components for wiring connection. This patent inverts the approach by allowing the wiring to contact the gate electrode directly at its original level, eliminating the need for elevation structures and reducing contact resistance interfaces.

Inventive Principle:
Principle #13The other way round (Inversion)

2Reliability

If contact plugs are formed to connect components, then electrical connection is achieved, but electrical shorts may occur between gate structure and contact plug structure

Engineering Contradiction:
Improveelectrical connectionVSAvoidelectrical short
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the contact plug structure that was causing electrical shorts between the gate electrode and contact plug. By removing this component and establishing direct wiring-to-gate-electrode contact, the source of the electrical short is eliminated while electrical connection is preserved.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If via structures are formed to connect contact plugs to upper wirings, then electrical connection is established, but total resistance increases due to contact resistance

Engineering Contradiction:
Improveelectrical connectionVSAvoidtotal resistance
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent removes the via structure from the electrical path between the gate electrode and upper wiring. The wiring directly contacts the gate electrode, eliminating the via structure and its associated contact resistance, thereby reducing total resistance while maintaining electrical connection.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20230352547A1Semiconductor devices
Publication Date: 2023.11.02 SAMSUNG ELECTRONICS CO LTD
  • US20230352547A1 patent drawing
  • US20230352547A1 patent drawing
  • US20230352547A1 patent drawing

AI summary

A semiconductor device includes first and second gate structures, first and second contact plug structures and a first wiring on a substrate. The first and second source/drain layers are formed on portions of the substrate adjacent to the first and second gate structures, respectively. The first and second contact plug structures are formed on the first and second source/drain layers, respectively. The first wiring contacts an upper surface of the first gate structure. The first gate structure includes a first gate electrode and a first gate insulation pattern on a lower surface and a sidewall of the first gate electrode. The second gate structure includes a second gate electrode and a second gate insulation pattern on a lower surface and a sidewall of the second gate electrode. The upper surface of the second gate electrode is lower than an upper surface of the first gate electrode.