Semiconductor Structure Ground Line Segmentation
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Solution Overview
Problem
In semiconductor memory devices, the body effect caused by extra loading in circuit designs can significantly change the threshold voltage of transistors, necessitating a reduction in this effect while minimizing the area occupied by ground lines, which traditionally requires large metal ground lines that interfere with bit lines and increase manufacturing costs.
Innovation Solution
A semiconductor structure with a specific arrangement of ground lines and bit lines, where multiple bit lines share a single ground line, reducing the area occupied by ground lines and maintaining electrical properties by using a staircase structure and alternating bit line stacks, allowing for efficient reduction of body effect without altering the electrical characteristics of adjacent bit lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If huge metal ground lines are introduced to diminish the body effect, then the body effect is reduced, but the effective area of the circuit is reduced and the manufacturing cost increases
Solution Approach 1:
The patent divides the ground line system into multiple smaller ground lines distributed among stacking blocks, rather than using a single huge ground line. Each stacking block is assigned at least one ground line, segmenting the ground function across multiple locations to reduce overall area occupation while maintaining body effect mitigation.
Solution Approach 2:
The patent transitions from a two-dimensional planar ground line arrangement to a three-dimensional vertical stacking structure. Ground lines are integrated into the vertical stacking blocks, utilizing the third dimension to provide ground functionality without occupying additional horizontal circuit area.
2Reliability
If huge metal ground lines are introduced to diminish the body effect, then the body effect is reduced, but the bit line electrical characteristics are changed by loading and coupling effects
Solution Approach 1:
The patent applies ground lines locally to specific stacking blocks rather than using continuous huge ground lines. Each stacking block receives appropriate ground line allocation, providing localized body effect mitigation without creating extensive coupling zones that would affect bit line characteristics.
Solution Approach 2:
By segmenting the ground line system into discrete portions associated with individual stacking blocks, the patent reduces the overall coupling effect on bit lines while maintaining sufficient ground reference for body effect reduction in each local region.
3Reliability
If traditional huge ground lines are used, then body effect is diminished, but dummy bit lines must be designed which increases manufacturing cost
Solution Approach 1:
The segmented ground line approach integrated into stacking blocks eliminates the need for dummy bit lines. By providing distributed ground references at appropriate locations, the patent achieves body effect reduction without requiring additional dummy structures, thereby reducing manufacturing complexity and cost.
Data Source
AI summary
A semiconductor device comprises a plurality of stacking blocks and a plurality of conductive lines. Each stacking blocks comprises two opposite finger VG structures. Each finger VG structure includes a staircase structure and a plurality of bit line stacks. The staircase structure is perpendicular to the bit line stacks, and the bit line stacks of the two opposite finger VG structures are arranged alternately. The conductive lines is disposed over the stacking blocks at interval. The direction of the conductive lines is parallel to a direction of the bit line stacks. The conductive lines include a plurality of bit lines and a plurality of ground lines, and each stacking block includes at least one ground line.