3D Semiconductor Memory Fabrication Using Hard Mask Planarization
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Solution Overview
Problem
The high cost and restrictive nature of increasing integration density in two-dimensional semiconductor memory devices, and the need for cost-effective and reliable manufacturing processes for three-dimensional semiconductor memory devices.
Innovation Solution
A method for fabricating semiconductor devices involving the formation of a lower structure with sequentially stacked etch target layers, a first hard mask layer with a level top surface, and a second hard mask pattern, where the first hard mask pattern is used as an etch mask to etch the stack, with repeated size reduction and ultrasonic wave application in the coating and curing of polymer compositions to improve planarization and etching precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor memory devices use fine patterns to increase integration density, then integration density is improved, but manufacturing cost increases and process complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cells are stacked in the vertical direction, allowing integration density to increase without requiring finer lateral patterns. This dimensional change enables higher density while using existing lithography capabilities, thereby reducing manufacturing cost.
Solution Approach 2:
The memory device is divided into multiple stacked layers or cells in the vertical direction. Each stack contains multiple memory cells that can be independently addressed, allowing the total storage capacity to scale with the number of stacks rather than requiring continuously smaller feature sizes in the plane.
2Quantity of substance
If two-dimensional semiconductor memory devices use fine patterns to increase integration density, then integration density is improved, but process complexity increases
Solution Approach 1:
By moving to three-dimensional stacking, the patent reduces reliance on advanced lithography processes. The vertical stacking approach uses standard lithography to create larger lateral features, then builds complexity in the vertical dimension through sequential deposition and etching processes, thereby reducing overall process complexity.
3Quantity of substance
If three-dimensional semiconductor memory devices are manufactured, then integration density is improved, but manufacturing precision requirements increase
Solution Approach 1:
Hard mask layers are formed with planarized top surfaces before the etching process. This preliminary planarization ensures that subsequent etching processes start from a uniform surface, improving etching precision and reducing variability. The hard mask layers serve as precise templates that define the lateral dimensions of the etched features.
Solution Approach 2:
Hard mask layers are introduced as intermediary layers between the lithography pattern and the etch target. These mask layers provide a robust, precisely patterned interface that protects the underlying structures during etching and enables high-precision lateral definition without directly exposing the sensitive memory cell structures to the etch process.
4Manufacturing precision
If hard mask layers are formed with planarized surfaces, then etching precision is improved, but process complexity increases
Solution Approach 1:
The hard mask layer serves multiple functions: it provides the lateral pattern definition, creates a planarized surface for subsequent processing, and acts as a protective barrier during etching. By combining these functions into a single layer formation step, the patent achieves high etching precision without proportionally increasing process complexity.
Solution Approach 2:
The formation of the hard mask layer combines pattern transfer and surface planarization into a single process step. The top surface of the hard mask layer is formed to be substantially planar, simultaneously achieving precise lateral definition and a uniform surface for subsequent etching operations, thereby reducing the need for separate planarization steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces fabrication costs, minimizes defective patterns, and enhances integration density by simplifying the process and improving etching precision, making it suitable for mass production of three-dimensional semiconductor memory devices.
Implementation Method 1
an ultrasonic wave may be applied to the composition in at least one step of coating a composition for the first hard mask layer on the lower structure and curing the composition
Data Source
AI summary
A method for fabricating a semiconductor device is provided. In the method, a first hard mask layer is formed on a stepped structure. The first hard mask layer has a level top surface and thickness sufficient to etch the structure. A second hard mask pattern is formed on the first hard mask layer. The first hard mask layer is etched using the second hard mask pattern. Size dispersion of the patterns may be reduced by the first hard mask layer.