Semiconductor High-Speed Testing via Internal Clock Generation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The development of high-speed semiconductor apparatuses outpaces the development of test equipment, making it difficult to perform high-speed tests efficiently due to the expense and slow development speed of test equipment.

Innovation Solution

A system comprising a first and second semiconductor apparatus, where the first semiconductor apparatus generates a high-frequency internal clock signal from a lower-frequency external clock signal and outputs reference data, and the second semiconductor apparatus receives this data to generate an error detection signal, enabling high-speed data communication and testing even in a low-speed operation environment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If test equipment is used to test high-speed semiconductor apparatus, then testing can be performed, but test equipment development is slow and expensive

Engineering Contradiction:
Improvetesting speedVSAvoidtest equipment complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The semiconductor apparatus under test performs self-testing by using its own internal resources (clock signal generation, data transmission, error detection) to test itself, eliminating the need for external high-speed test equipment. The apparatus generates its own high-frequency clock signal, transmits test data, and detects errors internally.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The semiconductor apparatus is designed to perform multiple functions: normal operation and self-testing. The same data transmission paths and processing units used for normal operation are also used for testing, making the test equipment universal and eliminating the need for separate dedicated test equipment.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Speed

If high-frequency clock signal is used for data communication, then data communication speed increases, but test equipment must operate at the same high speed which is expensive

Engineering Contradiction:
Improvedata communication speedVSAvoidtesting reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The system implements feedback through error detection signals that are generated and returned to the transmitting apparatus. This feedback mechanism allows verification of high-speed data transmission reliability by detecting transmission errors and providing information about transmission quality.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

Error detection signals act as intermediaries between the transmitted data and the verification process. These signals carry information about transmission integrity without requiring the test equipment to directly process the high-speed data stream, thus maintaining reliability while reducing test equipment speed requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of operation

If external low-speed clock signal is provided, then test environment is simplified, but internal high-speed operation is needed

Engineering Contradiction:
Improvetest environment easeVSAvoidclock signal frequency adaptability
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

The semiconductor apparatus changes the frequency parameter of the clock signal internally by generating a high-frequency clock signal from a lower-frequency external clock signal. This frequency multiplication allows the apparatus to operate at high speeds while the external test environment can use lower, more manageable frequencies.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system separates the clock signal frequency dimensions: external connections operate at one frequency level (lower, easier to manage) while internal operations operate at another frequency level (higher, enables fast processing). This dimensional separation allows each part of the system to operate optimally in its own frequency domain.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10529437B2Semiconductor apparatus and system relating to performing a high speed test in a low speed operation environment
Publication Date: 2020.01.07 SK HYNIX INC
  • US10529437B2 patent drawing
  • US10529437B2 patent drawing
  • US10529437B2 patent drawing

AI summary

A system may include a first semiconductor apparatus and a second semiconductor apparatus. Each of the first and second semiconductor apparatuses may receive reference data and a first clock signal. The first semiconductor apparatus may generate a first internal clock signal from the first clock signal, and may output the reference data as transmission data based on the first internal clock signal. The second semiconductor apparatus may generate a second internal clock signal from the first clock signal, and may receive the transmission data based on the second internal clock signal. The second semiconductor apparatus may generate an error detection signal based on the received data and the reference data.