Semiconductor Hole Alignment via Concurrent Etching
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Solution Overview
Problem
In 3-D semiconductor structures, the non-self-aligned holes for word lines (WLs) and bit lines (BLs) require a process window for alignment, leading to increased cell size and inaccuracy, which complicates the manufacturing process.
Innovation Solution
A method is developed to form a semiconductor structure with first and second holes that are equally spaced apart in at least one direction, allowing them to be formed concurrently through a stack of alternate sacrificial and insulating layers, enabling exact alignment and reducing the need for a separate alignment process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If holes for WLs replacement and holes for BLs are formed separately with non-self-aligned process, then alignment process window is required, but cell size increases and alignment inaccuracy occurs
Solution Approach 1:
The patent combines the formation of holes for WLs replacement and holes for BLs into a single self-aligned process step. By using the same hole structure for both purposes and forming them concurrently through the stack, the invention eliminates the need for separate alignment processes, thereby improving alignment accuracy while reducing cell size.
Solution Approach 2:
The invention implements self-alignment where the hole structure serves both functions automatically without requiring external alignment processes. The holes are formed to be equally spaced apart in at least one direction, allowing the structure to self-align the WLs replacement holes and BLs holes, thus eliminating process window requirements and reducing cell dimensions.
2Productivity
If separate processes are used for forming holes for WLs replacement and holes for BLs, then alignment process window is needed, but manufacturing complexity and time increase
Solution Approach 1:
The patent merges the formation of holes for WLs replacement and holes for BLs into a single integrated process step. This consolidation reduces the total number of process steps, eliminates the need for separate alignment procedures, and simplifies the overall manufacturing flow, thereby improving productivity while reducing process complexity.
Solution Approach 2:
The invention establishes the hole structure in advance with predetermined equal spacing in at least one direction, enabling both WLs replacement and BLs formation to proceed simultaneously without requiring subsequent alignment adjustments. This preliminary structuring simplifies the manufacturing process and enhances productivity.
Data Source
AI summary
A semiconductor structure and a method for manufacturing the same are provided. The method comprises the following steps. First, a stack of alternate sacrificial layers and insulating layers is formed on a bottom layer on a substrate. Then, a plurality of first holes and a plurality of second holes are formed through the stack concurrently. In the semiconductor structure as formed by the embodied method, the first holes and the second holes are equally spaced apart from each other at least in an arranged direction.