Impedance Calibration for Semiconductor Data Output Buffers
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Solution Overview
Problem
Existing semiconductor devices face challenges in precise impedance calibration due to variations in transistor impedance caused by voltage changes, especially when the reference potential is set to a level offset from half the power supply potential, leading to deviations in impedance values of data output buffers.
Innovation Solution
The semiconductor device incorporates a plurality of transistors connected in parallel, with an impedance control circuit that adjusts the impedance of second transistor units to match an external resistance, ensuring the impedance of the first transistor unit corresponds to the target impedance, even at varying source-drain voltages, by using an external resistance with a higher impedance value to achieve precise calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the reference potential is set to one half of the power supply potential for impedance calibration, then the calibration circuit can operate with a fixed reference level, but the calibration precision deteriorates when the reference potential needs to be offset from one half due to specification requirements
Solution Approach 1:
The patent applies dynamics by making the reference potential adjustable rather than fixed. The reference potential generation circuit can set the reference potential to different voltage levels (including offset from one half of power supply potential) depending on the required impedance calibration specifications, allowing the system to adapt to different calibration requirements while maintaining precision.
Solution Approach 2:
The patent changes the parameter of reference potential voltage level dynamically. By allowing the reference potential to be set to various voltage levels (not just fixed at one half of power supply potential), the system can adjust the calibration parameters to match different impedance requirements, thereby resolving the contradiction between ease of operation and measurement precision.
2Measurement precision
If the impedance of transistor units is adjusted to match external resistance for calibration, then the impedance calibration precision is improved, but the impedance values deviate when source-drain voltage varies from calibration conditions
Solution Approach 1:
The patent applies feedback by using the calibration terminal to continuously monitor the impedance of the transistor units and adjust the impedance control signals accordingly. This closed-loop feedback mechanism ensures that the impedance values remain stable and match the target impedance even when source-drain voltage varies, preventing deviation from calibration conditions.
Solution Approach 2:
The patent performs preliminary impedance calibration by adjusting the transistor unit impedances to match the external resistance before normal operation. This preliminary action establishes accurate baseline impedance values that can then be maintained through feedback control during subsequent operations with varying source-drain voltages.
3Adaptability or versatility
If multiple transistor units are used for impedance calibration, then the impedance adjustment range is improved, but the device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the impedance calibration function into multiple independent transistor units (first, second, third transistor units with different impedances). Each transistor unit can be independently controlled through separate control signals, allowing flexible combination to achieve a wide impedance adjustment range while keeping each individual unit relatively simple.
Solution Approach 2:
The patent makes the calibration circuit universal by designing transistor units that can serve multiple functions: they can be individually adjusted for precise impedance matching, combined in different configurations for various impedance ranges, and used for both calibration and normal data output operations. This multi-functionality reduces overall device complexity despite having multiple units.
Data Source
AI summary
Disclosed herein is a semiconductor device that includes a first transistor unit coupled to the data terminal, and a plurality of second transistor units coupled to the calibration terminal. The first transistor unit includes a plurality of first transistors having a first conductivity type connected in parallel to each other so that an impedance of the first transistor unit is adjustable. Each of the second transistor units includes a plurality of second transistors having the first conductivity type connected in parallel to each other so that an impedance of each of the second transistor units is adjustable. The semiconductor device further includes an impedance control circuit that reflects the impedance of each of the second transistor units to the first transistor unit.