Semiconductor Device Inductance Reduction via 3D Wiring
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices face challenges in sufficiently reducing inductance between positive (P) and negative (N) terminals, which hinders surge voltage suppression and the full performance of semiconductor elements due to limitations in current wiring member layouts and conductive plate configurations.
Innovation Solution
A semiconductor device design featuring a plurality of semiconductor elements with specific electrode connections, conductive plates, and strategically arranged main current wiring members, including branch portions and extension portions, to minimize inductance and enhance performance by preventing current flow under semiconductor elements and using magnetic flux cancellation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wiring member layouts and conductive plate configurations are used, then device structure is simple, but inductance between P and N terminals cannot be sufficiently reduced
Solution Approach 1:
The patent transitions from planar wiring layouts to a three-dimensional configuration where the first main current wiring member extends outside the case and the second main current wiring member is positioned to face it across the case boundary. This spatial arrangement in multiple dimensions enables magnetic flux cancellation and significantly reduces inductance between P and N terminals, directly addressing the surge voltage suppression requirement.
Solution Approach 2:
The first main current wiring member is divided into multiple segments: an extension portion outside the case, a first extension portion inside the case, and branch portions connecting to semiconductor elements. This segmentation allows optimized current flow paths and facilitates the complex three-dimensional arrangement needed for low inductance while maintaining manufacturability.
2Reliability
If wiring members are extended outside the case with branch portions, then inductance is reduced, but manufacturing complexity increases
Solution Approach 1:
The first main current wiring member integrates multiple functions into a single component: it serves as both the P terminal connection and the N terminal connection through its extension and branch portions. The wiring member combines extension portions for external connection, internal portions for mounting on conductive plates, and branch portions for semiconductor element connections, reducing the number of separate components and assembly steps.
3Reliability
If current flow paths are made parallel and adjacent in opposite directions, then inductance is reduced, but device area increases
Solution Approach 1:
Instead of expanding the planar area to accommodate parallel current paths, the patent utilizes the third dimension by extending wiring members outside the case boundary. The first main current wiring member extends beyond the case side surface, and the second main current wiring member is positioned to face it, creating a compact three-dimensional current loop that reduces inductance without increasing the circuit board footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces inductance between P and N terminals, suppressing voltage surges and overheating, thereby enhancing the performance and reliability of semiconductor elements while maintaining a compact device size.
Implementation Method 1
there is known a technique in which a current loop is formed by providing the V− terminal higher than the V+ terminal, so as to reduce inductance with magnetic flux cancellation
Data Source
AI summary
A semiconductor device includes a group of semiconductor elements each having a collector electrode and emitter electrode, a conductive plate electrically connected to the collector electrodes, and a case housing these. The semiconductor device further includes an OUT terminal and a P terminal respectively extending across the case so as to be disposed inside and outside the case. The OUT terminal includes an extension portion which includes a branch base portion extending across one side of the case toward the inside of the case and a pair of branch portions branching off from the branch base portion and being electrically connected to the emitter electrodes. The P terminal includes an extension portion sandwiched between the pair of branch portions, the P terminal being electrically connected to the conductive plate.