Semiconductor Package Inductor Layout via Molding Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor package structures face challenges in optimizing the layout between inductors and redistribution layers, as inductors limit the layout region and cause crosstalk affecting the semiconductor die, while also restricting inductance performance.
Innovation Solution
The semiconductor package structure features a molding layer covering the semiconductor die's back and sidewall surfaces, with the inductor positioned within the molding layer and extending between its surfaces, allowing for a larger inductor size and separate redistribution layer placement without interference, enabling strong inductance performance and increased layout flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the inductor is disposed over the semiconductor die, then the inductor occupies layout region, but the layout region for redistribution layer is limited and crosstalk affects the semiconductor die
Solution Approach 1:
The inductor is repositioned from the traditional planar layout over the semiconductor die to a vertical configuration extending through the molding layer. This dimensional transition allows the inductor to utilize the Z-axis space, thereby freeing up the XY-plane layout region for the redistribution layer while maintaining adequate inductance performance through increased inductor size in the vertical dimension.
2Reliability
If the inductor is disposed over the semiconductor die, then the inductor occupies layout region, but crosstalk from the inductor affects the semiconductor die
Solution Approach 1:
The inductor is extracted from its traditional position directly over the semiconductor die and relocated to extend through the molding layer. This separation physically removes the inductor from proximity to the semiconductor die, thereby eliminating the crosstalk interference while preserving the inductor's functional performance through its enhanced vertical configuration.
3Reliability
If the inductor size is increased for better inductance performance, then inductance performance is improved, but the layout region is further limited
Solution Approach 1:
The inductor design transitions from a planar two-dimensional layout to a three-dimensional vertical structure extending through the molding layer. This enables the inductor to achieve larger effective area and improved inductance performance by utilizing the vertical dimension, while the horizontal footprint remains compact, thus not further limiting the layout region for other components.
Data Source
AI summary
A semiconductor package structure and a method for forming the same are disclosed. The semiconductor package structure includes a semiconductor die, a molding layer and an inductor. The semiconductor die includes an active surface, a back surface and a sidewall surface between the active surface and the back surface. The molding layer covers the back surface and the sidewall surface of the semiconductor die. The inductor is in the molding layer. The sidewall surface of the semiconductor die faces toward the inductor.