Semiconductor Device Insulating Layer Thermal Expansion Gradient
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Solution Overview
Problem
The reliability of semiconductor devices is compromised due to stress generated at the connection interfaces caused by differing thermal expansion coefficients of various materials when subjected to temperature cyclic loads, leading to reduced performance and durability.
Innovation Solution
A semiconductor device configuration is implemented where a first insulating layer with a linear expansion coefficient equal to or larger than the base material layer, and a second insulating layer with a coefficient equal to or smaller than the first, are used between the base material layer and the semiconductor chip, ensuring a balanced expansion coefficient sequence to mitigate stress and improve reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple materials with different thermal expansion coefficients are used in the semiconductor device, then the device can be manufactured with various functional layers, but stress is generated at connection interfaces under temperature cyclic loads, reducing reliability
Solution Approach 1:
The patent changes the physical parameter of thermal expansion coefficient by selecting insulating layers with specific coefficient ranges. The first insulating layer has a coefficient equal to or larger than the base material layer, and the second insulating layer has a coefficient equal to or smaller than the first insulating layer, creating a gradient that accommodates thermal stress
Solution Approach 2:
The patent uses composite material structure with multiple insulating layers having different thermal expansion coefficients. This composite approach allows the system to handle thermal stress through the layered structure while maintaining the necessary functional properties of each layer
2Device complexity
If a single insulating layer is used between the base material layer and semiconductor chip, then the structure is simple, but stress concentration occurs at the connection interfaces under temperature cyclic loads
Solution Approach 1:
The patent divides the insulating layer into multiple segments (first insulating layer and second insulating layer) with different thermal expansion coefficients. This segmentation allows each layer to handle different portions of the thermal stress, preventing stress concentration that would occur with a single uniform layer
Solution Approach 2:
The patent changes the parameter of thermal expansion coefficient across the insulating layer structure. By setting the first insulating layer's coefficient equal to or larger than the base material layer, and the second insulating layer's coefficient equal to or smaller than the first, the structure creates a thermal expansion gradient that distributes stress
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces stress and peeling-off issues at the connection interfaces, enhancing the overall reliability and durability of the semiconductor device under temperature cyclic loads.
Implementation Method 1
a linear expansion coefficient of the first insulating layer is equal to or larger than a linear expansion coefficient of the base material layer, the linear expansion coefficient of the first insulating layer is equal to or smaller than a linear expansion coefficient of the second insulating layer, and the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the second insulating layer
Data Source
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AI summary
In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2CR) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.