Semiconductor Device Insulating Layer Local Quality
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Solution Overview
Problem
Semiconductor devices with microbumps as external connection terminals face issues such as air bubble interference during plating, increased susceptibility to opening defects, loss of plating seed layer, and reduced durability against ion migration due to the thin insulating layer, leading to reliability concerns.
Innovation Solution
A semiconductor device design featuring a two-step insulating layer structure with a thinner layer covering the conductor where the external connection terminal is formed and a thicker layer elsewhere, reducing the aspect ratio of openings and enhancing air bubble removal, exposure margin, and thermal stability, thereby improving the reliability and durability against ion migration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the insulating layer is made thin to match the reduced size of microbumps, then the device miniaturization is achieved, but ion migration durability is reduced
Solution Approach 1:
The insulating layer is designed with non-uniform thickness: thinner region (first thickness) under the external connection terminal for miniaturization, and thicker region (second thickness greater than first) in the periphery for ion migration protection. This local differentiation allows simultaneous achievement of device miniaturization and reliability maintenance.
2Volume of moving object
If the insulating layer is made thin to enable device miniaturization, then the manufacturing scale is reduced, but air bubble removal during plating becomes difficult
Solution Approach 1:
The insulating layer thickness is locally optimized: thin region enables device miniaturization, while the thicker peripheral region reduces the aspect ratio of openings, facilitating air bubble removal during plating processes.
3Volume of moving object
If the insulating layer is made thin to achieve microbump configuration, then the device size is reduced, but opening defect susceptibility increases
Solution Approach 1:
The insulating layer is configured with different thicknesses in different regions: the thinner portion enables microbump integration while the thicker peripheral portion provides sufficient exposure margin during photolithography, reducing opening defect susceptibility.
4Volume of moving object
If the insulating layer is made thin to match microbump size, then the device miniaturization is achieved, but plating seed layer loss occurs
Solution Approach 1:
The insulating layer thickness is locally differentiated to provide adequate coverage in the peripheral region where the plating seed layer is formed, preventing seed layer loss while maintaining thin profile under the microbump area for miniaturization.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a conductor provided on a main surface of the semiconductor substrate, an insulating layer disposed to cover a surface of the conductor and having a recess from a surface thereof towards the conductor, the recess having an opening provided at a bottom portion of the recess and exposing a portion of the conductor, and an external connection terminal connected to the portion of the conductor exposed from the opening. In a plan view of the semiconductor device, the external connection terminal covers the entire opening, and the entire external connection terminal is within the recess.