Semiconductor Insulation Layer Design for Thermal Stress Mitigation
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Solution Overview
Problem
Semiconductor devices with flip-chip bonding type face thermal distortion issues due to differing linear expansion coefficients between the semiconductor chip and external conductive members, leading to potential cracks in the insulation layer.
Innovation Solution
A semiconductor device design featuring a dual-layer insulation structure with a retracted portion and shield portion in the second insulation layer, along with a protection layer and conductive bonding members, which alleviates thermal stress by reducing constriction and preventing excessive stress on the insulation layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If flip-chip bonding is used to improve production efficiency and reduce resistance, then the semiconductor chip and external conductive member are disposed very close to each other, but thermal distortion occurs due to different linear expansion coefficients causing cracks in the insulation layer
Solution Approach 1:
The insulation layer is divided into multiple sections: a first insulation layer portion covering part of the terminal layer, and a second insulation layer portion covering the first insulation layer portion. This segmentation allows different regions of the insulation layer to have different thicknesses and mechanical properties, enabling the structure to accommodate thermal expansion differences between the semiconductor chip and external conductive member while maintaining electrical insulation.
Solution Approach 2:
The patent applies local quality by creating a specific insulation layer configuration where the second insulation layer portion has different properties compared to the first insulation layer portion. The second portion extends beyond the terminal layer in plan view, providing enhanced coverage and stress distribution in critical areas, while the first portion maintains direct contact with the terminal layer for electrical insulation. This localized differentiation addresses the thermal distortion problem without compromising overall insulation effectiveness.
2Ease of manufacture
If the semiconductor chip and external conductive member are disposed close to each other via solder bump, then production efficiency is improved, but thermal distortion causes undesired crack in the insulation layer
Solution Approach 1:
The patent implements beforehand cushioning by designing the insulation layer structure to anticipate and accommodate thermal expansion differences before they cause damage. The second insulation layer portion extends beyond the terminal layer boundaries, creating a buffer zone that absorbs and distributes thermal stress. This pre-configured cushioning structure prevents cracks from forming during thermal cycling without requiring complex manufacturing processes or additional components.
3Device complexity
If a simple insulation layer structure is used, then device complexity is reduced, but the insulation layer cannot withstand thermal stress from linear expansion differences
Solution Approach 1:
The patent applies dimensionality change by extending the second insulation layer portion beyond the terminal layer boundaries in the plan view direction. This creates an L-shaped or T-shaped insulation structure that provides both vertical coverage over the terminal layer and horizontal extension into the surrounding area. The multi-dimensional configuration distributes thermal stress across a larger area and prevents stress concentration at critical interfaces, thereby enhancing thermal stress resistance without significantly increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The configuration effectively suppresses the occurrence of cracks in the insulation layer, as demonstrated by thermal cycle tests showing reduced crack formation even after multiple cycles, enhancing the device's reliability and durability.
Implementation Method 1
a conductive bonding member that connects the inner conductive member and the outer conductive member
Implementation Method 2
the semiconductor chip and an external conductive member on a substrate may be significantly different in linear expansion coefficient from each other. By the flip-chip bonding, the semiconductor chip and the external conductive member are disposed very close to each other via a solder bump, and thus thermal distortion may often occur
Data Source
AI summary
A semiconductor device includes a semiconductor chip, a terminal layer, an insulation layer with an opening, a protection layer with an opening, an inner conductive member, an outer conductive member, and a conductive bonding member. The insulation layer includes a first insulation layer, and a second insulation layer opposite to the functional surface of the chip with respect to the first insulation layer. The second insulation layer includes a shield portion overlapping with the terminal layer in plan view, and a retracted portion not overlapping with the terminal layer in plan view. A back surface of the retracted portion of the second insulation layer is more distant from the functional surface in a z-direction than is the main surface of the terminal layer that is opposite to the functional surface.