Semiconductor Device Inter-Pillar Channel Layer for High Density
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in achieving higher storage capacity and performance due to limitations in channel length and chip density.
Innovation Solution
The semiconductor device features a channel layer disposed between two conductive pillars, reducing channel length and increasing chip density by altering the stacking configuration of conductive and insulating layers, with the channel layer coupled to both pillars and surrounding the memory structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel layer is arranged outside the first conductive pillar and the second conductive pillar and surrounds them, then the channel layer can be continuously formed, but the channel length becomes longer which reduces device performance
Solution Approach 1:
The channel layer is repositioned from a surrounding configuration to an inter-pillar configuration, utilizing the space between the first and second conductive pillars. This spatial reconfiguration in a different dimensional arrangement reduces the channel length from extending around the pillars to only spanning the gap between them, thereby improving device performance while maintaining continuous channel formation.
Solution Approach 2:
Instead of the conventional approach where the channel layer surrounds the conductive pillars, this invention inverts the arrangement by placing the channel layer between the pillars. This inversion of the spatial relationship fundamentally reduces the channel length and improves device performance.
2Quantity of substance
If the channel layer surrounds the conductive pillars, then the structure is simpler to fabricate, but the chip density is reduced
Solution Approach 1:
The channel layer is repositioned from a surrounding configuration to an inter-pillar configuration, utilizing the space between the first and second conductive pillars. This spatial reconfiguration in a different dimensional arrangement reduces the channel length, thereby improving device performance while maintaining continuous channel formation.
Solution Approach 2:
Instead of the conventional approach where the channel layer surrounds the conductive pillars, this invention inverts the arrangement by placing the channel layer between the pillars. This inversion of the spatial relationship fundamentally reduces the channel length and improves device performance.
Data Source
AI summary
A semiconductor device includes a stack and a plurality of memory strings. The stack is formed on a substrate, and the stack includes conductive layers and insulating layers alternately stacked. The memory strings penetrate the stack along a first direction. Each of the memory strings includes a first conductive pillar, a second conductive pillar, a channel layer and a memory structure. The first conductive pillar and the second conductive pillar extend along the first direction, respectively, and electrically isolated to each other. The channel layer extends along the first direction. The channel layer is disposed between the first conductive pillar and the second conductive pillar, and the channel layer is coupled to the first conductive pillar and the second conductive pillar. The memory structure surrounds the first conductive pillar, the second conductive pillar and the channel layer.