Semiconductor Interconnect Structure for Wire Bonding Reliability
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Solution Overview
Problem
The use of low-dielectric-constant insulating films in semiconductor devices leads to mechanical weakness, causing cracks and separation during wire bonding and probing, especially with the recent trend of shrinking inter-pad pitch and increasing load per unit area, which degrades the yield of final products.
Innovation Solution
A semiconductor device configuration with a multi-layered interconnect structure that includes an upper and lower multi-layered interconnect structure separated by an intermediate insulating film, where the upper structure has a higher ratio of area occupied by interconnects and vias, and the lower structure has a smaller ratio of area occupied by vias, allowing for gradual absorption of load and impact, thereby preventing insulating interlayer separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-dielectric-constant insulating films are used for insulating interlayers, then the electrical performance is improved, but the mechanical strength deteriorates causing crack or separation
Solution Approach 1:
The patent applies composite materials by combining low-k insulating films with reinforcing interconnect patterns (copper or aluminum) formed in specific geometries. The interconnect patterns are embedded within the insulating interlayers to create a composite structure that maintains the electrical performance of low-k materials while adding mechanical reinforcement to prevent crack and separation issues during wire bonding and probing processes.
Solution Approach 2:
The patent segments the insulating interlayer into multiple regions by forming reinforcing interconnect patterns that divide the low-k material into smaller sections. These segmented regions are mechanically supported by the interconnect patterns, preventing the entire insulating layer from cracking or separating under stress during bonding processes.
2Strength
If the area ratio of copper in the upper copper interconnect layer is increased to moderate load, then the resistance against impact is improved, but the device complexity increases
Solution Approach 1:
The patent applies local quality by varying the area ratio of copper interconnects in different layers. Specifically, the upper copper interconnect layer has a larger area ratio (higher copper content) to absorb impact loads during wire bonding, while lower layers have progressively smaller area ratios. This gradient structure provides mechanical reinforcement where needed without unnecessarily complicating the entire interconnect system.
Solution Approach 2:
The patent resolves complexity by transitioning from a single-layer reinforcement approach to a multi-layer gradient structure. Instead of uniformly increasing copper area throughout all layers, the solution distributes reinforcement across multiple dimensions (layers) with varying densities, achieving impact resistance through spatial distribution rather than uniform complexity.
3Productivity
If the diameter of bonding wires is shrunk to match inter-pad pitch shrinkage, then the productivity is improved, but the load per unit area increases causing separation
Solution Approach 1:
The patent applies beforehand cushioning by incorporating reinforcing interconnect patterns and gradient copper structures in advance of the wire bonding process. These pre-built reinforcement structures are designed to absorb and distribute the concentrated loads that will be applied during bonding with thinner wires, preventing separation before it occurs.
Solution Approach 2:
The patent implements preliminary action by pre-forming the multi-layer gradient interconnect structure with varying copper area ratios before the wire bonding process. This preliminary reinforcement structure is prepared in advance to handle the increased stress from thinner bonding wires, enabling high-productivity bonding without causing separation.
Data Source
AI summary
In a semiconductor device, a lower multi-layered interconnect structure, an intermediate via-level insulating interlayer, and an upper multi-layered interconnect structure are stacked in this order in a region overlapped with a bonding pad in a plan view; upper interconnects and vias of the upper multi-layered interconnect structure are formed so as to be connected to the bonding pad in the pad placement region; the intermediate via-level insulating interlayer has no electro-conductive material layer, which connect the interconnects or vias in the upper multi-layered interconnect structure with interconnects or vias in the lower multi-layered interconnect structure, formed therein; and the ratio of area occupied by the vias in the via-level insulating interlayers contained in the lower multi-layered interconnect structure is smaller than the ratio of area occupied by the vias in the via-level insulating interlayers contained in the upper multi-layered interconnect structure.