Semiconductor Package Conductive Interconnect Void Elimination
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Solution Overview
Problem
The miniaturization of semiconductor package structures leads to gaps between dies and solder bumps becoming narrower, making it difficult for molded under-fill materials to completely fill these gaps, resulting in voids and reliability issues due to incomplete filling and high-temperature processing effects.
Innovation Solution
A semiconductor package design that includes a core layer with a conductive interconnect penetrating through it to directly contact a conductive pad on a semiconductor chip, eliminating the need for solder bumps and under-fill layers, and using an adhesive layer for attachment, thereby improving electrical connections and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder bumps and under-fill layers are used to connect semiconductor chips, then electrical connections can be established, but voids form due to incomplete filling of narrow gaps and high-temperature processing causes reliability issues
Solution Approach 1:
The patent removes the solder bump and under-fill layer from the connection structure, replacing them with a conductive interconnect that penetrates through the core layer. This extraction eliminates the void formation problem associated with incomplete gap filling while maintaining electrical connection functionality.
Solution Approach 2:
The conductive interconnect acts as an intermediary element that penetrates through the core layer to directly contact the conductive pad on the semiconductor chip. This intermediary structure provides a reliable electrical connection pathway without requiring solder bumps or under-fill materials, thereby avoiding void formation and high-temperature processing issues.
2Reliability
If solder bumps are used for electrical connection, then conductivity is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts and eliminates the solder bump component from the connection architecture, replacing it with a simplified conductive interconnect integrated into the core layer. This reduction in components decreases manufacturing complexity and cost while maintaining reliable electrical connection.
Solution Approach 2:
The conductive interconnect merges the functions of electrical connection and structural support into a single integrated element that penetrates the core layer. This consolidation eliminates the need for separate solder bumps and under-fill layers, thereby reducing device complexity and manufacturing steps.
3Strength
If adhesive layers are used for chip attachment, then mechanical bonding is achieved, but additional manufacturing steps are required
Solution Approach 1:
The patent combines the adhesive function with the conductive interconnect structure, where the adhesive layer is integrated into the same manufacturing process that forms the conductive pathways. This merging of functions maintains strong mechanical bonding while streamlining the manufacturing process by reducing separate attachment steps.
Data Source
AI summary
A semiconductor package includes a core layer, a conductive interconnect and a semiconductor chip. The core layer has a top surface and a bottom surface opposite to the top surface. The conductive interconnect penetrates through the core layer. The conductive interconnect has a top surface and a bottom surface respectively exposed from the top surface and the bottom surface of the core layer. The semiconductor chip is disposed on the top surface of the core layer. The semiconductor chip includes a conductive pad, and the top surface of the conductive interconnect directly contacts the conductive pad.