Semiconductor Interconnect Etch Selectivity via Dual Subtractive Process
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in manufacturing semiconductor devices lies in reliably producing nanometer and smaller features, as the shrinking dimensions of integrated circuit components require precise materials and processes to maintain satisfactory electrical performance, especially in very large scale integration (VLSI) and ultra large-scale integration (ULSI) interconnect technology.
Innovation Solution
A dual subtractive etch process is employed, involving the formation of titanium nitride and ruthenium layers with specific etch stop layers and gas mixtures, including oxygen and chlorine, to achieve high etch selectivity and minimize oxidation, allowing for precise patterning and profile control of metal interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used for ruthenium layers, then etching can proceed, but etch selectivity is insufficient and oxidation of underlying layers occurs
Solution Approach 1:
The patent changes the chemical parameters of the etching process by using a gas mixture containing oxygen (30-100 sccm) and chlorine (10-50 sccm) with specific flow rate ratios. This parameter change enables selective etching of ruthenium while controlling oxidation through the balanced gas composition, achieving both high etch selectivity and protection of underlying layers
Solution Approach 2:
The patent employs a composite gas mixture approach, combining oxygen and chlorine in specific proportions to create an etching environment that simultaneously provides selective ruthenium etching and oxidation control. The composite nature of the gas mixture allows synergistic effects that neither gas alone could achieve
2Productivity
If feature dimensions are reduced to nanometer and smaller scales, then integration density increases, but manufacturing reliability and electrical performance deteriorate
Solution Approach 1:
The patent applies local quality by creating precisely controlled etching conditions specific to ruthenium layers, using tailored gas mixtures and parameter settings that are optimized for the local requirements of nanoscale interconnect fabrication. This localized optimization ensures reliable electrical performance at reduced dimensions
3Manufacturing precision
If etching continues for longer duration to ensure complete pattern transfer, then patterning completeness improves, but oxidation of underlying layers increases
Solution Approach 1:
The patent implements feedback control through real-time monitoring of etch depth and pattern transfer progress, allowing dynamic adjustment of etching parameters. This feedback mechanism enables complete pattern transfer while preventing excessive oxidation by stopping the process at the optimal point
Solution Approach 2:
The patent uses parameter changes in the gas flow rates during the etching process to control the balance between etching rate and oxidation. By adjusting the oxygen-to-chlorine ratio dynamically, the process achieves complete pattern transfer while minimizing oxidation of underlying layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of reliable metal interconnects with high etch selectivity and controlled profiles, ensuring proper patterning and reducing oxidation of underlying layers, thus addressing the challenges of miniaturization in semiconductor manufacturing.
Implementation Method 1
the removal comprises performing an oxygen-containing ash process
Implementation Method 2
The transferring comprises etching the second ruthenium layer using a gas mixture comprising oxygen and chlorine
Implementation Method 3
determining an end point at a second time using optical emission spectrometry
Data Source
AI summary
Generally, embodiments described herein relate to methods for manufacturing an interconnect structure for semiconductor devices, such as in a dual subtractive etch process. An embodiment is a method for semiconductor processing. A titanium nitride layer is formed over a substrate. A hardmask layer is formed over the titanium nitride layer. The hardmask layer is patterned into a pattern. The pattern is transferred to the titanium nitride layer, where the transferring comprises etching the titanium nitride layer. After transferring the pattern to the titanium nitride layer, the hardmask layer is removed, where the removal comprises performing an oxygen-containing ash process.