Multi-Directional Semiconductor Interconnect Mesh for Voltage Drop Reduction
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Solution Overview
Problem
Conventional semiconductor devices with power supply interconnects in a mesh structure experience directional voltage drops due to resistance differences between interconnect layers, limiting the reduction of voltage drops and chip area efficiency.
Innovation Solution
A semiconductor device with a first interconnect layer and a second interconnect layer, where both layers include interconnects extending in multiple directions, with specific arrangements and connections between interconnect blocks to reduce resistance and voltage drop, allowing for a two-dimensionally formed power supply interconnect structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If power supply interconnects are arranged in a simple mesh structure with one-dimensional extension in each layer, then the interconnect layout is simple and easy to manufacture, but directional voltage drops occur due to resistance differences between layers
Solution Approach 1:
The patent transforms the conventional one-dimensional interconnect extension in each layer into a two-dimensional mesh structure where interconnects extend in both lateral and vertical directions. This dimensional change creates multiple current paths and eliminates directional voltage drops by distributing current flow across two dimensions, thereby resolving the contradiction between manufacturing simplicity and voltage distribution uniformity.
Solution Approach 2:
The patent employs a composite interconnect structure combining two different interconnect layers (nth layer and (n+1)th layer) with different resistance characteristics. By forming a mesh pattern that integrates both layers with interconnects extending in perpendicular directions, the structure compensates for resistance differences between layers, achieving uniform voltage distribution while maintaining ease of manufacture.
2Device complexity
If power supply interconnects extend in only one direction per layer, then the interconnect structure is simple, but voltage drop increases in the direction toward the central portion of the chip
Solution Approach 1:
The patent introduces a second dimension to interconnect extension by forming mesh patterns where interconnects in the (n+1)th layer extend vertically relative to those in the nth layer. This creates multiple current paths that reduce the effective resistance and voltage drop toward the chip center, while the mesh structure itself remains relatively simple to implement.
Solution Approach 2:
The patent divides the power supply interconnect system into two separate layers with interconnects extending in different directions. This segmentation allows each layer to be optimized independently while collectively providing multiple current paths that reduce overall voltage drop, balancing structural simplicity with energy efficiency.
3Adaptability or versatility
If resistance differs between nth layer and (n+1)th layer, then manufacturing can accommodate different thicknesses, but voltage drop becomes directional along the interconnect extension direction
Solution Approach 1:
The patent creates a composite interconnect system using two layers with different resistance characteristics resulting from different thicknesses. By forming a mesh structure where interconnects in each layer extend in perpendicular directions, the system leverages the resistance differences to balance voltage distribution across the chip, converting what would be a harmful effect into a beneficial one.
Solution Approach 2:
The patent intentionally utilizes the asymmetric resistance properties of the two interconnect layers by orienting interconnects in perpendicular directions. This asymmetric configuration ensures that the layer with higher resistance contributes less to voltage drop in its extension direction, while the other layer compensates, achieving overall voltage uniformity despite thickness variations.
Data Source
AI summary
A semiconductor device includes a first interconnect layer and a second interconnect layer provided above or under the first interconnect layer. The first interconnect layer includes a plurality of first interconnect blocks, and in each of the first interconnect blocks, a first interconnect has a first potential, and extends in at least two or more directions, and a second interconnect has a second potential, and extends in at least two or more directions. The second interconnect layer includes a third interconnect which electrically connects the first interconnect of one of a pair of adjacent first interconnect blocks and the first interconnect of the other of the pair of adjacent first interconnect blocks, and a fourth interconnect which electrically connects the second interconnect of one of the pair of adjacent first interconnect blocks and the second interconnect of the other of the pair of adjacent first interconnect blocks.