Semiconductor Interconnect Structure With Selective Tungsten Filling
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Solution Overview
Problem
As semiconductor devices continue to shrink, traditional aluminum metal interconnection technology struggles to meet the demands of modern integrated circuit development, with copper interconnect technology facing challenges due to increasing resistance and parasitic capacitance, necessitating improved metal interconnection line technology.
Innovation Solution
A semiconductor structure and formation method involving a substrate with a covering layer, an auxiliary layer, dielectric layers, and conductive layers, where the growth rate of the conductive material over the auxiliary layer is higher than over the covering layer, reducing the likelihood of premature closure of openings and enhancing performance by using tungsten-fluorine bonds for faster tungsten material formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper interconnect technology is used to meet the demands of modern integrated circuit development, then the interconnection performance is improved, but the resistance and parasitic capacitance of metal wires increase
Solution Approach 1:
The patent changes the material parameter from traditional copper to tungsten, and further introduces tungsten fluoride as an intermediate layer. This parameter change in material composition and chemical state enables better control of resistance and parasitic capacitance while maintaining interconnection performance
Solution Approach 2:
The patent employs a composite structure consisting of multiple layers including tungsten interconnect lines, tungsten fluoride intermediate layers, and dielectric materials. This composite material approach allows optimization of electrical properties by combining materials with complementary characteristics
2Adaptability or versatility
If the number of metal wiring layers is increased to support higher integration, then the interconnection capacity is improved, but the resistance and parasitic capacitance become more restrictive factors
Solution Approach 1:
The patent introduces a vertical dimension by stacking multiple metal wiring layers with alternating dielectric layers, creating a three-dimensional interconnect structure. This dimensional approach increases interconnection capacity while the tungsten fluoride intermediate layers help manage the electrical properties across layers
3Ease of manufacture
If conventional deposition processes are used to form conductive layers, then the manufacturing process is simple, but the growth rate uniformity and filling quality are poor
Solution Approach 1:
The patent introduces tungsten fluoride as an intermediary layer between the substrate and the tungsten interconnect material. This intermediate layer acts as a mediator that promotes uniform nucleation and growth of the conductive material, improving filling quality and growth rate uniformity while maintaining process feasibility
Solution Approach 2:
The tungsten fluoride intermediate layer is formed in advance before the main tungsten deposition process. This preliminary action prepares the surface with optimal chemical properties for subsequent material growth, ensuring uniform deposition and preventing defects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of semiconductor structures by reducing the chance of opening closure before full filling, leading to better conductivity and reduced defects, thus addressing the limitations of existing metal interconnection technologies.
Implementation Method 1
a first selective deposition process to form an auxiliary layer over a surface of the covering layer
Implementation Method 2
using tungsten-fluorine bonds for faster tungsten material formation
Data Source
AI summary
A semiconductor structure includes a substrate, a covering layer on the substrate, an auxiliary layer on the covering layer, a first dielectric layer on surfaces of the substrate and the auxiliary layer, and a conductive structure in the first dielectric layer. The semiconductor structure also includes a second dielectric layer on surfaces of the first dielectric layer and the conductive structure, a first opening in the second dielectric layer and the first dielectric layer, and a second opening in the second dielectric layer. The first opening exposes the auxiliary layer, and the second opening exposes the top surface of the conductive structure. A first conductive layer is in the first opening, and a second conductive layer is in the second opening. A growth rate of the first conductive layer over the auxiliary layer is higher than the growth rate of the first conductive layer over the covering layer.