Semiconductor Interconnect Structure Preventing Undercutting

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In semiconductor manufacturing, reentrant undercutting at the interface of metallic and anti-reflection coating layers leads to undesirable voids and potential lifting of aluminum layers, degrading semiconductor device yield.

Innovation Solution

A semiconductor structure comprising metallic pillars, protrusions, a capping layer, and a passivation layer, where the passivation layer is deposited on the sidewalls of the protrusions and capping layer, and the base is etched to form pillars, using a method that includes patterning a capping layer, depositing a passivation layer, and etching through trenches to prevent undercutting.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If conventional etching process is used to form conducting lines, then interconnect layers can be patterned, but reentrant undercutting occurs at the interface of metallic layer and anti-reflection coating layer

Engineering Contradiction:
Improveinterconnect layer patterningVSAvoidinterface geometry control
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

A mandrel structure is formed beforehand with a specific geometry featuring a top surface that is offset from its bottom surface. This preliminary structure guides the subsequent etching process to create the desired conductive line pattern while preventing reentrant undercutting by controlling the etch front propagation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The mandrel acts as an intermediary structure between the photoresist pattern and the final conductive line. It transfers the pattern while its specially designed geometry (offset top and bottom surfaces) mediates the etching process to prevent harmful undercutting at the metallic layer interface.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If reentrant undercutting is prevented, then void formation and aluminum layer lifting are avoided, but process complexity increases

Engineering Contradiction:
Improveinterconnect structure integrityVSAvoidmanufacturing process steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The mandrel structure is prepared in advance with the precise geometry needed to prevent undercutting. This preliminary action embeds the solution within a single etching step, avoiding the need for additional process steps to prevent void formation or aluminum layer lifting.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The mandrel structure serves multiple functions simultaneously: it defines the conductive line pattern, controls the etch front to prevent reentrant undercutting, and ensures proper interface geometry. This multi-functionality achieves reliability improvement without proportionally increasing process complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively prevents undercutting and void formation, enhancing the yield and reliability of semiconductor devices by ensuring a stable interconnect structure.

Implementation Method 1

depositing a passivation layer on sidewalls of the metallic protrusions and the capping layer

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

etching the base through the trenches to form a plurality of metallic pillars underlying the respective metallic protrusions

Methodology Applied
Scientific EffectPlasma Etching: Plasma

Data Source

PatentUS10777522B2Semiconductor structure and method of manufacturing the same
Publication Date: 2020.09.15 NAN YA TECH
  • US10777522B2 patent drawing
  • US10777522B2 patent drawing
  • US10777522B2 patent drawing

AI summary

The present disclosure provides a semiconductor structure and a method of manufacturing the semiconductor structure. The semiconductor structure includes a substrate, a plurality of metallic pillars, a plurality of metallic protrusions, a capping layer, and a passivation layer. The metallic pillars are disposed on the substrate. The metallic protrusions extend from an upper surface of the metallic pillars. The capping layer is disposed on the metallic protrusions. The passivation layer is disposed on sidewalls of the protrusions and the capping layer.