Semiconductor Interconnect Structure With Reduced Vertical Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor fabrication techniques require extensive vertical routing and additional metal layers to establish electrical connections between active semiconductor regions, leading to increased routing material and space usage, which can result in unwanted capacitances.
Innovation Solution
The use of conductive structures, such as metal lines, directly over active semiconductor regions to form electrical connections without the need for additional vertical routing or BEOL processes, reducing the amount of routing material and space required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If extensive vertical routing and additional metal layers are used to establish electrical connections between active semiconductor regions, then reliable electrical connections are achieved, but routing material and space usage increase leading to unwanted capacitances
Solution Approach 1:
The patent extracts and eliminates the unnecessary vertical routing components from the conventional interconnect structure. By using conductive structures that extend laterally from gate contacts to source/drain regions within the same planar layer, the invention removes the need for multiple vertical metal layers and via connections, thereby reducing routing material quantity while maintaining electrical connection reliability
Solution Approach 2:
The patent transitions from a vertical three-dimensional routing approach to a lateral two-dimensional routing approach. The conductive structures are formed to extend horizontally across the semiconductor surface rather than stacking vertically, changing the dimensionality of the interconnect path and reducing the quantity of routing material needed
2Reliability
If extensive vertical routing and additional metal layers are used to establish electrical connections between active semiconductor regions, then electrical connections are established, but space usage increases
Solution Approach 1:
The patent removes the vertical routing components including intermediate metal layers and via structures from the conventional interconnect design. The conductive structures are configured to provide electrical connections using only lateral extensions within the gate contact layer, extracting unnecessary spatial elements and reducing overall routing space usage
Solution Approach 2:
The patent merges the functions of gate contacts, interconnect lines, and contact pads into a single integrated conductive structure. This consolidation eliminates the need for separate vertical routing layers and via connections, thereby reducing the total space required for electrical interconnections while maintaining connection reliability
3Quantity of substance
If conductive structures are used directly over active semiconductor regions, then routing material and space are reduced, but manufacturing complexity may increase
Solution Approach 1:
The conductive structures are designed to perform multiple functions simultaneously: serving as gate contacts, interconnect lines, and contact pads for source/drain regions. This multi-functionality reduces the need for separate routing structures and simplifies the overall device architecture, offsetting any potential increases in manufacturing complexity through functional integration
Data Source
AI summary
Semiconductor structures and methods for forming a semiconductor structure are provided. The method includes forming a first active semiconductor region disposed in a first vertical level of the semiconductor structure, forming a second active semiconductor region disposed in the first vertical level, where the second active semiconductor region is separated from the first active semiconductor region by a distance in a first direction, forming a first conductive structure disposed in a second vertical level that is adjacent to the first vertical level. The first conductive structure extends along the first direction and electrically couples the first active semiconductor region to the second active semiconductor region.