3D Semiconductor Interconnect Voltage Drop Reduction
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Solution Overview
Problem
The miniaturization of semiconductor devices to achieve high speed and reliability poses design challenges due to reduced pattern widths, particularly in ensuring efficient power distribution and signal integrity in three-dimensional semiconductor memory devices.
Innovation Solution
The semiconductor device design includes a substrate with a cell array region and a peripheral circuit region, featuring interconnect lines and power lines at different heights, along with dummy interconnect lines to reduce voltage drop and enhance signal integrity, allowing for efficient power distribution and increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the pattern width is reduced to miniaturize the semiconductor device, then the device size is minimized, but the power distribution efficiency and signal integrity deteriorate
Solution Approach 1:
The patent transitions from two-dimensional planar interconnect布局 to three-dimensional stacked interconnect layers. Multiple interconnect lines are arranged vertically at different heights (first height, second height, third height) to provide redundant power distribution paths and improve signal integrity without increasing the footprint area, thus resolving the contradiction between miniaturization and reliability.
Solution Approach 2:
The power distribution network is segmented into multiple independent interconnect lines at different heights. Each interconnect line serves as a separate power distribution path, and dummy interconnect lines are added to further segment and balance the current distribution, reducing voltage drop while maintaining compact device dimensions.
2Reliability
If more interconnect lines are added to improve power distribution, then the voltage drop is reduced, but the device complexity increases
Solution Approach 1:
Multiple interconnect lines are merged into a unified three-dimensional power distribution network. The first, second, and third interconnect lines at different heights work together as an integrated system, sharing common contact holes and power lines, which reduces overall complexity compared to implementing separate two-dimensional networks for each layer.
Solution Approach 2:
Dummy interconnect lines are introduced that automatically balance the current distribution across the power network. These dummy lines self-adjust the electrical load distribution without requiring external control mechanisms, reducing voltage drop while adding minimal structural complexity.
Data Source
AI summary
A semiconductor device includes a substrate including a cell array region and a peripheral circuit region. The semiconductor device further includes a cell array disposed in the cell array region and including a plurality of cell strings connected to a bit line. The bit line extends in a first direction. The semiconductor device additionally includes a first cell row disposed in the peripheral circuit region and including a plurality of first cells arranged in a second direction crossing the first direction. The first and second directions being parallel to an upper surface of the substrate. The semiconductor device further includes a plurality of first interconnect lines each having a longitudinal axis in the first direction and connected to the plurality of first cells, and a plurality of first power lines extending in the second direction and connected to the plurality of first cells through the first interconnect lines.