Semiconductor Package Intermediate Connection Structure

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Solution Overview

Problem

Semiconductor packages face issues with cracks in external connection terminals due to differences in thermal expansion with external devices like printed circuit boards, leading to stress and fatigue-related problems.

Innovation Solution

A semiconductor package structure is developed with an intermediate connection structure that includes a semiconductor chip, a protective layer, an insulating pattern, and an external connection terminal, which reduces thermal expansion differences with external devices, enhancing stress distribution and crack resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a semiconductor package is mounted on a board, then electrical connection is achieved, but thermal expansion difference causes cracks in external connection terminals

Engineering Contradiction:
Improvecrack resistance of external connection terminalVSAvoidthermal expansion difference
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces an intermediate connection structure comprising an insulating pattern and external pad between the semiconductor chip and board. This intermediate structure acts as a mediator that absorbs and distributes thermal stress, reducing the direct thermal expansion difference between the semiconductor package and board, thereby preventing cracks in external connection terminals.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The intermediate connection structure uses composite materials including insulating patterns and external pads with specific thickness ratios. The composite structure combines materials with different thermal expansion properties to create a gradient that gradually transitions from the semiconductor chip to the board, reducing thermal stress concentration.

Inventive Principle:
Principle #40Composite materials

2Strength

If the insulating pattern and external pad have sufficient thickness, then stress distribution is improved, but device complexity increases

Engineering Contradiction:
Improvestress distribution capabilityVSAvoidstructure complexity
Core Design Contradiction:
StrengthVSDevice complexity

Solution Approach 1:

The patent specifies optimal thickness parameters for the insulating pattern and external pad, where the external pad thickness is 0.5 to 2.0 times the insulating pattern thickness. By optimizing these dimensional parameters, the structure achieves adequate stress distribution without excessive complexity, balancing mechanical strength and manufacturing simplicity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed structure effectively minimizes cracks in external connection terminals by matching thermal expansion coefficients with external devices, improving reliability and durability of semiconductor packages.

Implementation Method 1

a difference in thermal expansion (CTE1≠CTE2, provided that CTE is an abbreviation of Coefficient of Expansion and refers to the coefficient of thermal expansion) occurs between the semiconductor package 10 and the board 20

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS11476211B2Semiconductor package and manufacturing method thereof
Publication Date: 2022.10.18 NEPES CO LTD
  • US11476211B2 patent drawing
  • US11476211B2 patent drawing
  • US11476211B2 patent drawing

AI summary

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a lower structure including a semiconductor chip having a chip terminal; an external connection terminal connecting the semiconductor chip to an external device; and an intermediate connection structure including an upper surface and a lower surface opposite to the upper surface, and positioned between the lower structure and the external connection terminal.