Semiconductor Package Interposer Segmentation for Integration Density
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Solution Overview
Problem
Existing semiconductor packages, such as the CoWoS structure, face limitations in integration density and packaging efficiency, particularly in advanced applications like cloud computing and supercomputing, where smaller feature sizes and reduced package area are required but not fully met by current technologies.
Innovation Solution
The semiconductor package design incorporates a 'chip on fan-out on substrate' (CoFoS) structure, where interposers are used as chiplets with smaller sizes, and semiconductor dies are connected through bridge structures, allowing for improved integration density and yield by embedding interposers within a dielectric encapsulation and forming redistribution layers for electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional CoWoS structure is used, then electrical connectivity is achieved, but integration density and packaging efficiency are limited
Solution Approach 1:
The patent divides the traditional monolithic interposer into multiple smaller interposer segments (first interposer and second interposer). Each segment can be independently manufactured and tested, then assembled together with semiconductor dies to form the complete package. This segmentation enables higher integration density while managing structural complexity through modular design.
Solution Approach 2:
The patent implements a nested structure where semiconductor dies are mounted on interposer segments, which are then embedded within a dielectric encapsulation layer. The dielectric encapsulation itself is nested within the overall package structure, creating multiple hierarchical levels of nesting that improve packaging efficiency and integration density.
2Manufacturing precision
If smaller feature sizes are used, then more devices can be integrated, but manufacturing difficulty increases
Solution Approach 1:
By segmenting the interposer into smaller manageable pieces, each segment can be manufactured with smaller feature sizes using existing fabrication processes. This avoids the need to manufacture entire large interposers with fine features, reducing manufacturing difficulty while achieving high integration density through the assembled structure.
Solution Approach 2:
The interposer segments are manufactured and prepared in advance before final assembly with the semiconductor dies. This preliminary fabrication allows optimization of manufacturing processes for each segment independently, making it easier to achieve small feature sizes without compounding the difficulty across the entire package structure.
3Reliability
If larger packages are used, then existing structures are adequate, but area occupation increases
Solution Approach 1:
The nested arrangement of dies on interposers within dielectric encapsulation allows the package components to be compactly organized in a hierarchical structure. This nesting reduces the overall package area compared to traditional planar layouts while maintaining adequate spacing and connectivity for reliability.
Solution Approach 2:
The patent transitions from traditional two-dimensional package layouts to a more three-dimensional nested structure where components are arranged vertically and horizontally. The dielectric encapsulation provides a matrix that organizes interposers and dies in multiple dimensions, reducing the footprint area while preserving functional adequacy.
Data Source
AI summary
A semiconductor package includes a first interposer, a second interposer, a first die, a second die and at least one bridge structure. The first interposer and the second interposer are embedded by a first dielectric encapsulation. The first die is disposed over and electrically connected to the first interposer. The second die is disposed over and electrically connected to the second interposer. The at least one bridge structure is disposed between the first die and the second die.