Semiconductor IPD Alignment via Conductive Bridge
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Solution Overview
Problem
Conventional methods for forming integrated passive devices (IPDs) externally to semiconductor dies are costly and prone to misalignment, leading to reduced reliability and increased leakage current, especially in high-current applications.
Innovation Solution
A method involving the formation of a first and second inductor over a semiconductor die, with a conductive bridge and fan-out redistribution layer to align and connect IPDs, reducing leakage current and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If IPDs are formed externally to semiconductor die using conventional methods, then manufacturing flexibility is improved, but manufacturing precision deteriorates due to misalignment
Solution Approach 1:
The patent applies preliminary action by forming alignment marks and reference structures on the semiconductor die before the IPDs are externally formed. This pre-established reference system enables precise alignment during subsequent IPD fabrication, resolving the contradiction between external formation flexibility and alignment precision.
Solution Approach 2:
The patent introduces an intermediary alignment mark structure that mediates between the semiconductor die and externally formed IPDs. These alignment marks serve as a common reference framework, enabling precise positioning of IPDs relative to the die without requiring direct mechanical coupling, thus maintaining both flexibility and precision.
2Device complexity
If IPDs are formed externally to semiconductor die, then device complexity is reduced, but reliability deteriorates due to leakage current
Solution Approach 1:
The patent extracts the IPD formation process from the semiconductor die fabrication process, allowing IPDs to be formed separately on a different substrate or at a different time. This separation reduces the complexity of the integrated manufacturing process while maintaining reliability through dedicated IPD optimization and reduced interference with die fabrication.
Solution Approach 2:
The patent introduces an intermediary insulating layer and controlled interface structure between the externally formed IPDs and the semiconductor die. This intermediary structure provides electrical isolation that prevents leakage current paths while maintaining necessary electrical connections through controlled vias, thus resolving the reliability issue.
3Ease of manufacture
If IPDs are formed externally to semiconductor die, then manufacturing cost is reduced, but manufacturing precision deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-forming alignment marks, reference patterns, and interface structures on the semiconductor die before IPD fabrication. This pre-prepared reference system enables cost-effective external IPD formation while maintaining high alignment precision through automated optical or mechanical alignment to the pre-existing marks.
Solution Approach 2:
The patent replaces complex mechanical alignment systems with optical or electromagnetic alignment methods that use pre-formed marks on the die. This substitution reduces manufacturing cost by using simpler, more automated alignment techniques while maintaining or improving precision through optical field-based positioning.
Data Source
AI summary
A semiconductor device has a first semiconductor die. A first inductor is formed over the first semiconductor die. A second inductor is formed over the first inductor and aligned with the first inductor. An insulating layer is formed over the first semiconductor die and the first and second inductors. A conductive bridge is formed over the insulating layer and electrically connected between the second inductor and the first semiconductor die. In one embodiment, the semiconductor device has a second semiconductor die and a conductive layer is formed between the first and second semiconductor die. In another embodiment, a capacitor is formed over the first semiconductor die. In another embodiment, the insulating layer has a first thickness over a footprint of the first semiconductor die and a second thickness less than the first thickness outside the footprint of the first semiconductor die.