Semiconductor Device Joint Surface Abnormality Detection Circuit
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Solution Overview
Problem
Existing semiconductor devices with stacked structures cannot effectively detect abnormalities outside the pixel array unit, as these abnormalities do not affect the output timing of pulse signals, limiting the detection target location's degree of freedom.
Innovation Solution
A semiconductor device with a connection line wired across multiple substrates and a detection circuit that detects abnormalities based on the energization state of the connection line, using resistors, transistors, and logic gates to identify issues at any joint surface location, and a test system that includes a detection unit for the detection circuit's failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pulse signal timing analysis is used for failure detection, then pixel array unit failures can be detected, but the detection target location is limited and degree of freedom is low
Solution Approach 1:
The semiconductor device is divided into multiple substrates with distinct functional regions (pixel array unit, row drive unit, failure detection unit). The failure detection unit is further segmented into multiple detection circuits, each capable of detecting abnormalities in different regions through dedicated connection lines. This segmentation enables targeted detection of specific substrate regions while maintaining the ability to detect both pixel array failures and other abnormalities.
Solution Approach 2:
The failure detection unit is designed with multiple detection circuits that can perform multiple detection functions. Each detection circuit can detect abnormalities in different regions (pixel array, row drive unit, or other areas) by monitoring different connection lines. This multi-functionality allows a single failure detection unit to provide comprehensive coverage across the entire semiconductor device, improving both detection precision and location flexibility.
2Device complexity
If detection is limited to pixel array unit through pulse signal analysis, then detection method is simple, but abnormalities in other areas cannot be detected
Solution Approach 1:
The invention merges multiple detection approaches into a unified failure detection unit. The pulse signal timing analysis method (original simple method) is combined with new voltage-based detection methods that monitor connection lines between substrates. Multiple detection circuits are integrated to simultaneously perform different detection functions, creating a comprehensive detection system that maintains operational simplicity while expanding detection coverage to include all substrate regions.
Solution Approach 2:
The failure detection unit is designed as a multi-functional system that can detect various types of abnormalities using different methods. It can perform pulse signal timing analysis for pixel array detection, voltage level detection for connection line abnormalities, and other detection modes. This universality ensures comprehensive reliability coverage while keeping each individual detection method relatively simple and manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the detection of abnormalities at any location between semiconductor substrates, improving the degree of freedom in detection target locations and ensuring the reliability of the semiconductor device by identifying peeling, short-circuiting, or other joint surface issues.
Implementation Method 1
a detection circuit configured to detect the presence or absence of an abnormality in a joint surface of the plurality of semiconductor substrates based on an energization state of the connection line
Data Source
AI summary
The degree of freedom of an abnormality detection target location in a solid-state imaging device in which a plurality of substrates are joined is improved. A semiconductor device includes a connection line and a detection circuit. A plurality of semiconductor substrates are joined in the semiconductor device. Then, in the semiconductor device, the connection line is wired across the plurality of semiconductor substrates. The detection circuit detects the presence or absence of an abnormality in a joint surface of the plurality of semiconductor substrates based on an energization state of the connection line when enable has been set by a predetermined control signal.