Non-destructive Semiconductor Junction Layout via Laser Scanning
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Solution Overview
Problem
Current reverse engineering methods for semiconductor integrated circuits are invasive and destructive, requiring the de-layering of devices to analyze their inner workings, which is costly, complicated, and not suitable for complex modern chips.
Innovation Solution
A non-destructive method involving the application of an electrical stimulus and irradiation with external sources to induce electron-hole pairs in semiconductor junctions, allowing for the determination of junction layouts and inference of functional cells and connectivity without physically disassembling the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If de-layering is used to analyze semiconductor device structure, then structural information is obtained, but the device is destroyed and significant effort and equipment are required
Solution Approach 1:
The patent replaces mechanical de-layering with electrical measurement techniques. By applying electrical stimuli and measuring responses, the system obtains structural and functional information without physical disassembly, thus preserving device integrity while achieving reverse engineering goals
Solution Approach 2:
The patent introduces an intermediary measurement system that uses electrical stimuli and response analysis as a mediator between the investigator and the device structure. This intermediary approach allows information extraction without direct physical contact or destruction of the device layers
2Loss of information
If full circuit extraction is performed to obtain complete schematic, then detailed circuit information is obtained, but the process is costly, complicated and destructive
Solution Approach 1:
The patent extracts only the essential functional information needed for reverse engineering purposes rather than performing complete circuit extraction. By focusing on obtaining netlist information and functional connectivity through electrical measurements, it avoids the complexity and cost of full manual circuit extraction while still achieving the primary reverse engineering objectives
Solution Approach 2:
The patent applies partial action by performing measurements on a subset of device behaviors and responses rather than attempting to characterize every aspect of the circuit. This selective approach obtains sufficient information for reverse engineering without the exhaustive effort of complete circuit extraction
3Manufacturing precision
If de-layering is performed to maintain surface planarity, then accurate layer analysis is achieved, but multiple recipes and methods are required increasing complexity
Solution Approach 1:
The patent replaces the complex mechanical and chemical de-layering processes with electrical measurement techniques. By using electrical stimuli and response analysis, it achieves layer and junction information extraction without requiring surface planarity maintenance or multiple specialized removal recipes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the non-destructive analysis of semiconductor devices, maintaining their operational state and providing detailed insights into functional cells and interconnectivity, facilitating a more efficient and cost-effective reverse engineering process.
Implementation Method 1
irradiating a surface of the semiconductor device by an external source capable of inducing electron-hole pairs in semiconductor junctions of the semiconductor device resulting in observable electric current
Data Source
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Figure 3A~3B
AI summary
Processes and systems for use in reverse engineering integrated circuits determine functionality through analysis of junctions responding to external radiation. Semiconductor devices include a number of p-n junctions grouped according to interconnected functional cells. A surface of the semiconductor device is illuminated by radiation, e.g., by a laser or an electron beam, producing electron-hole pairs. Such pairs give rise to detectable currents that can be used to determine locations of irradiated junctions. By scanning a surface of the device in such a manner, a layout of at least some of the junctions can be obtained. The layout can be used to identify functional cells according to a lookup process. By selectively providing input test vectors to the device and repeating the scanning process, first level functional cells can be identified. A netlist of interconnected functional cells can thus be determined and expanded by repeating the process with different test vectors.