Semiconductor Chip Lamination Resin Sealing and Dicing
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Solution Overview
Problem
The existing methods for manufacturing semiconductor devices with high miniaturization and integration, such as NAND-type flash memories, face challenges in achieving a compact size and satisfactory surface finish due to the need for large carrier substrates and inefficient dicing processes.
Innovation Solution
A semiconductor device manufacturing method involving the lamination of semiconductor chips between two substrates, where the chips are bonded, sealed with resin, and then cut using a dicing blade, allowing for discrete piece separation while minimizing package size and improving surface finish through precise resin application and reflow processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a member for preventing outflow of sealing material is provided on the carrier substrate, then sealing material can be contained, but the package size increases
Solution Approach 1:
The invention extracts and eliminates the separate member for preventing outflow of sealing material from the carrier substrate. Instead, the sealing material is contained by the structure formed by the lowermost chip, uppermost chip, and their respective pad electrodes, which naturally form containment boundaries without requiring additional components.
Solution Approach 2:
The pad electrodes serve multiple functions: they provide electrical connection between chips and simultaneously act as boundaries for containing sealing material. The lowermost chip and uppermost chip not only serve as interface chips for electrical connection but also define the containment structure for sealing material, eliminating the need for dedicated containment members.
2Productivity
If dicing is performed using a blade, then discrete pieces can be separated, but the surface finish is less than satisfactory
Solution Approach 1:
The invention performs preliminary sealing of all spaces between chips and substrates with sealing material before the dicing process. This preliminary sealing action ensures that the blade during dicing does not encounter unsealed gaps or voids, thereby achieving satisfactory surface finish on the cut surfaces while still enabling discrete piece separation.
3Ease of manufacture
If wire-bonding is used for signal transmission, then communication between chips is established, but signal transmission speed is limited
Solution Approach 1:
The invention replaces the mechanical wire-bonding system with a direct pad electrode contact system. Instead of using wire bonds to connect chips, the pad electrodes of adjacent chips are positioned to make direct contact, eliminating the intermediate wire connection. This substitution of the connection mechanism enables faster signal transmission while maintaining ease of manufacture through the lamination process.
4Reliability
If the carrier substrate is enlarged to accommodate the member for preventing outflow, then sealing material containment is improved, but the package size increases
Solution Approach 1:
The invention extracts and removes the separate containment member from the design. The sealing material containment is achieved through the natural boundaries formed by the chip structures and pad electrodes themselves, eliminating the need to enlarge the carrier substrate for containment purposes.
Solution Approach 2:
The invention creates localized containment structures at each chip interface using the pad electrodes and chip boundaries. Instead of requiring a large carrier substrate with a global containment member, the sealing material is contained locally at each interface between chips and substrates through the structured arrangement of pad electrodes and chip edges.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the production of compact semiconductor devices with improved surface finish and reduced thermal stress, achieving cost savings and increased reliability by eliminating the need for mold sealing and simplifying the manufacturing process.
Implementation Method 1
flowing resin from the side of the first substrate toward the second substrate to seal spaces between the first and second semiconductor chips and between the lamination and the second substrate
Implementation Method 2
providing electrical connections between the respective electrode pads by a reflow process
Data Source
AI summary
According to one embodiment a method is provided including positioning and bonding a plurality of first semiconductor chips in a coplanar relation on a first substrate, laminating at least a plurality of second semiconductor chips on the first semiconductor chips, cutting the first substrate for separation into a discrete chip lamination, aligning an electrode pad provided on a surface of the discrete lamination with an electrode pad on a second substrate, and temporarily connecting the electrode pads on the lamination and the second substrate in an opposing relation to the first substrate, providing electrical connection between the electrode pads by a reflow process, flowing a liquid resin from the side of the first substrate towards the second substrate to seal the chip lamination and spaces between the chip lamination and the first and second substrate, and cutting the chip lamination to form a discrete device.